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[RFC] using coherent icache feature in flush_idcache_range
From: |
Nicholas Piggin |
Subject: |
[RFC] using coherent icache feature in flush_idcache_range |
Date: |
Tue, 15 Jun 2021 14:51:55 +1000 |
I've had this patch lying around for quite a while, eagerly wrote it
when I was profiling something and saw flush_idcache_range right near
the top of profiles, but I wasn't able to reproduce it (maybe a bad
or just lucky profile). But I don't have the heart to throw it away
because it seems like a good thing to do in general.
Thoughts? Is there anything particularly icache update intensive that
might benefit (particularly that flushes large ranges)?
Thanks,
Nick
---
include/qemu/cacheflush.h | 4 ++++
util/cacheflush.c | 8 ++++++++
util/cacheinfo.c | 16 ++++++++++++++--
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h
index ae20bcda73..8befa537b0 100644
--- a/include/qemu/cacheflush.h
+++ b/include/qemu/cacheflush.h
@@ -28,6 +28,10 @@ static inline void flush_idcache_range(uintptr_t rx,
uintptr_t rw, size_t len)
#else
+#if defined(__powerpc__)
+bool have_coherent_icache;
+#endif
+
void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len);
#endif
diff --git a/util/cacheflush.c b/util/cacheflush.c
index 933355b0c9..cbc5147e2e 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -108,6 +108,14 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw,
size_t len)
b = rw & ~(dsize - 1);
e = (rw + len + dsize - 1) & ~(dsize - 1);
+
+ if (have_coherent_icache) {
+ asm volatile ("sync" : : : "memory");
+ asm volatile ("icbi 0,%0" : : "r"(b) : "memory");
+ asm volatile ("isync" : : : "memory");
+ return;
+ }
+
for (p = b; p < e; p += dsize) {
asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
}
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index b182f0b693..e903118be9 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -132,18 +132,30 @@ static void arch_cache_info(int *isize, int *dsize)
}
}
-#elif defined(_ARCH_PPC) && defined(__linux__)
-# include "elf.h"
+#elif defined(__powerpc__)
+bool have_coherent_icache = false;
+
+# if defined(_ARCH_PPC) && defined(__linux__)
+# include "elf.h"
static void arch_cache_info(int *isize, int *dsize)
{
+# ifdef PPC_FEATURE_ICACHE_SNOOP
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+# endif
+
if (*isize == 0) {
*isize = qemu_getauxval(AT_ICACHEBSIZE);
}
if (*dsize == 0) {
*dsize = qemu_getauxval(AT_DCACHEBSIZE);
}
+
+# ifdef PPC_FEATURE_ICACHE_SNOOP
+ have_coherent_icache = (hwcap & PPC_FEATURE_ICACHE_SNOOP) != 0;
+# endif
}
+# endif
#else
static void arch_cache_info(int *isize, int *dsize) { }
--
2.23.0
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