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[PATCH v6 09/14] target/ppc: Implement prefixed integer store instructio
From: |
matheus . ferst |
Subject: |
[PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions |
Date: |
Tue, 1 Jun 2021 16:35:23 -0300 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 12 ++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 547bd1736f..72c5944a53 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+### Fixed-Point Store Instructions
+
+PSTW 000001 10 0--.-- .................. \
+ 100100 ..... ..... ................ @PLS_D
+PSTB 000001 10 0--.-- .................. \
+ 100110 ..... ..... ................ @PLS_D
+PSTH 000001 10 0--.-- .................. \
+ 101100 ..... ..... ................ @PLS_D
+
+PSTD 000001 00 0--.-- .................. \
+ 111101 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index adeee33289..2d2d874146 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
TRANS(STBU, do_ldst_D, true, true, MO_UB)
TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
/* Store Halfword */
TRANS(STH, do_ldst_D, false, true, MO_UW)
TRANS(STHX, do_ldst_X, false, true, MO_UW)
TRANS(STHU, do_ldst_D, true, true, MO_UW)
TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
/* Store Word */
TRANS(STW, do_ldst_D, false, true, MO_UL)
TRANS(STWX, do_ldst_X, false, true, MO_UL)
TRANS(STWU, do_ldst_D, true, true, MO_UL)
TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
/* Store Doubleword */
TRANS64(STD, do_ldst_D, false, true, MO_Q)
TRANS64(STDX, do_ldst_X, false, true, MO_Q)
TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
- [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions, matheus . ferst, 2021/06/01
- [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions, matheus . ferst, 2021/06/01
- [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn, matheus . ferst, 2021/06/01
- [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns, matheus . ferst, 2021/06/01
- [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, matheus . ferst, 2021/06/01
- [PATCH v6 05/14] target/ppc: Implement PNOP, matheus . ferst, 2021/06/01
- [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree, matheus . ferst, 2021/06/01
- [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions, matheus . ferst, 2021/06/01
- [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree, matheus . ferst, 2021/06/01
- [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions,
matheus . ferst <=
- [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, matheus . ferst, 2021/06/01
- [PATCH v6 11/14] target/ppc: Implement cfuged instruction, matheus . ferst, 2021/06/01
- [PATCH v6 12/14] target/ppc: Implement vcfuged instruction, matheus . ferst, 2021/06/01
- [PATCH v6 13/14] target/ppc: Move addpcis to decodetree, matheus . ferst, 2021/06/01
- [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, matheus . ferst, 2021/06/01