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[PATCH 1/7] ppc/pnv: Add trace events for PCI event notification
From: |
Cédric Le Goater |
Subject: |
[PATCH 1/7] ppc/pnv: Add trace events for PCI event notification |
Date: |
Tue, 26 Jan 2021 18:10:53 +0100 |
On POWER9 systems, PHB controllers signal the XIVE interrupt controller
of a source interrupt notification using a store on a MMIO region. Add
traces for such events.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive.c | 3 +++
hw/pci-host/pnv_phb4.c | 3 +++
hw/intc/trace-events | 3 +++
hw/pci-host/trace-events | 3 +++
4 files changed, 12 insertions(+)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 5f69626b3a8d..ad43483612e5 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -24,6 +24,7 @@
#include "hw/ppc/xive_regs.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/ppc.h"
+#include "trace.h"
#include <libfdt.h>
@@ -1319,6 +1320,8 @@ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr
addr, uint64_t val)
uint8_t blk;
uint32_t idx;
+ trace_pnv_xive_ic_hw_trigger(addr, val);
+
if (val & XIVE_TRIGGER_END) {
xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64,
addr, val);
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 6328e985f81c..54f57c660a94 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -22,6 +22,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
+#include "trace.h"
#define phb_error(phb, fmt, ...) \
qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \
@@ -1257,6 +1258,8 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf,
uint32_t srcno)
uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
MemTxResult result;
+ trace_pnv_phb4_xive_notify(notif_port, data);
+
address_space_stq_be(&address_space_memory, notif_port, data,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 8ed397a0d587..45ddaf48df8e 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -236,3 +236,6 @@ xive_tctx_tm_write(uint64_t offset, unsigned int size,
uint64_t value) "@0x0x%"P
xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value)
"@0x0x%"PRIx64" sz=%d val=0x%" PRIx64
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found
NVT 0x%x/0x%x ring=0x%x"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END
0x%x/0x%x @0x0x%"PRIx64
+
+# pnv_xive.c
+pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64"
val=0x%"PRIx64
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index d19ca9aef6f7..7d8063ac4212 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -20,3 +20,6 @@ unin_data_write(uint64_t addr, unsigned len, uint64_t val)
"write addr 0x%"PRIx6
unin_data_read(uint64_t addr, unsigned len, uint64_t val) "read addr
0x%"PRIx64 " len %d val 0x%"PRIx64
unin_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
+
+# pnv_phb4.c
+pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64"
data=0x%"PRIx64
--
2.26.2
Re: [PATCH 4/7] ppc/pnv: Simplify pnv_bmc_create(), David Gibson, 2021/01/27
[PATCH 5/7] ppc/pnv: Discard internal BMC initialization when BMC is external, Cédric Le Goater, 2021/01/26
Re: [PATCH 5/7] ppc/pnv: Discard internal BMC initialization when BMC is external, David Gibson, 2021/01/27
[PATCH 1/7] ppc/pnv: Add trace events for PCI event notification,
Cédric Le Goater <=
[PATCH 6/7] ppc/pnv: Remove default disablement of the PNOR contents, Cédric Le Goater, 2021/01/26
[PATCH 7/7] ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR, Cédric Le Goater, 2021/01/26
[PATCH 3/7] ppc/pnv: Use skiboot addresses to load kernel and ramfs, Cédric Le Goater, 2021/01/26