[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: SPR implementation request.
From: |
BALATON Zoltan |
Subject: |
Re: SPR implementation request. |
Date: |
Sun, 21 Jun 2020 19:37:55 +0200 (CEST) |
User-agent: |
Alpine 2.22 (BSF 395 2020-01-19) |
On Sun, 21 Jun 2020, Jd Lyons wrote:
Would some knowledgeable person implement a few SPR’s to get OS X booting on
our emulated G5 CPU’s
qemu-system-ppc64 -M mac99 -m 1024 -hda ~/Leopard.img -serial stdio -d
guest_errors
=============================================================
OpenBIOS 1.1 [Oct 28 2019 17:09]
Configuration device id QEMU version 1 machine id 3
CPUs: 1
Memory: 1024M
UUID: 00000000-0000-0000-0000-000000000000
CPU type PowerPC,970FX
milliseconds isn't unique.
switching to new context:
call-method slw_update_keymap failed with error ffffffdf
call-method slw_update_keymap failed with error ffffffdf
Trying to write invalid spr 276 (0x114) at 00000000000b6db4
Trying to read invalid spr 277 (0x115) at 00000000000b6db8
Trying to read invalid spr 276 (0x114) at 00000000000b6dbc
Trying to write invalid spr 277 (0x115) at 00000000000b6dd8
Trying to write invalid spr 276 (0x114) at 00000000000b6ddc
Trying to read invalid spr 276 (0x114) at 00000000000b6de0
Trying to write invalid spr 277 (0x115) at 00000000000b6e8c
Trying to write invalid spr 276 (0x114) at 00000000000b6e90
Trying to read invalid spr 276 (0x114) at 00000000000b6e94
This:
http://fxr.watson.org/fxr/source/powerpc/include/spr.h
says:
148 #define SPR_SCOMC 0x114 /* ... SCOM Address Register (970)
*/
149 #define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */
invalid/unsupported opcode: 00 - 00 - 00 - 00 (00000000) 0000000000000000 0
Trying to write invalid spr 304 (0x130) at 0000000000003e14
Trying to read invalid spr 304 (0x130) at 0000000000003e38
567 #define SPR_DBSR 0x130 /* ..8 Debug Status Register */
568 #define DBSR_IDE 0x80000000 /* Imprecise debug event. */
569 #define DBSR_UDE 0x40000000 /* Unconditional debug
event. */
570 #define DBSR_MRR 0x30000000 /* Most recent Reset (mask).
*/
571 #define DBSR_ICMP 0x08000000 /* Instr. complete debug
event. */
572 #define DBSR_BRT 0x04000000 /* Branch taken debug event.
*/
573 #define DBSR_IRPT 0x02000000 /* Interrupt taken debug
event. */
574 #define DBSR_TRAP 0x01000000 /* Trap instr. debug event.
*/
575 #define DBSR_IAC1 0x00800000 /* Instr. address compare
#1. */
576 #define DBSR_IAC2 0x00400000 /* Instr. address compare
#2. */
577 #define DBSR_IAC3 0x00200000 /* Instr. address compare
#3. */
578 #define DBSR_IAC4 0x00100000 /* Instr. address compare
#4. */
579 #define DBSR_DAC1R 0x00080000 /* Data addr. read compare
#1. */
580 #define DBSR_DAC1W 0x00040000 /* Data addr. write compare
#1. */
581 #define DBSR_DAC2R 0x00020000 /* Data addr. read compare
#2. */
582 #define DBSR_DAC2W 0x00010000 /* Data addr. write compare
#2. */
583 #define DBSR_RET 0x00008000 /* Return debug event. */
But likely CPU manual has more detailed info on these, not sure if they
are needed though, it may go wrong for some other reason.
Regards,
BALATON Zoltan
Re: SPR implementation request.,
BALATON Zoltan <=