Re: [RFC PATCH v2] target/ppc: Enable hardfloat for PPC

[Richard Henderson]

On 3/1/20 4:13 PM, Programmingkid wrote:
> Ok, I was just looking at Intel's x87 chip documentation. It supports IEEE 
> 754 floating point operations and exception flags. This leads me to this 
> question. Would simply taking the host exception flags and using them to set 
> the PowerPC's FPU's flag be an acceptable solution to this problem? 

No.

The primary issue is the FPSCR.FI flag.  This is not an accumulative bit, per
ieee754, but per operation.

The "hardfloat" option works (with other targets) only with ieee745
accumulative exceptions, when the most common of those exceptions, inexact, has
already been raised.  And thus need not be raised a second time.

Per the PowerPC architecture, inexact must be recognized afresh for every
operation.  Which is cheap in hardware but expensive in software.

And once you're done with FI, FR has been and continues to be emulated 
incorrectly.


r~