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[PATCH v4 09/12] target/ppc: Correct RMLS table
From: |
David Gibson |
Subject: |
[PATCH v4 09/12] target/ppc: Correct RMLS table |
Date: |
Wed, 19 Feb 2020 13:14:06 +1100 |
The table of RMA limits based on the LPCR[RMLS] field is slightly wrong.
We're missing the RMLS == 0 => 256 GiB RMA option, which is available on
POWER8, so add that.
The comment that goes with the table is much more wrong. We *don't* filter
invalid RMLS values when writing the LPCR, and there's not really a
sensible way to do so. Furthermore, while in theory the set of RMLS values
is implementation dependent, it seems in practice the same set has been
available since around POWER4+ up until POWER8, the last model which
supports RMLS at all. So, correct that as well.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
---
target/ppc/mmu-hash64.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 4e6c1f722b..46690bc79b 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -762,12 +762,12 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
/*
- * This is the full 4 bits encoding of POWER8. Previous
- * CPUs only support a subset of these but the filtering
- * is done when writing LPCR
+ * In theory the meanings of RMLS values are implementation
+ * dependent. In practice, this seems to have been the set from
+ * POWER4+..POWER8, and RMLS is no longer supported in POWER9.
*/
const target_ulong rma_sizes[] = {
- [0] = 0,
+ [0] = 256 * GiB,
[1] = 16 * GiB,
[2] = 1 * GiB,
[3] = 64 * MiB,
--
2.24.1
- [PATCH v4 00/12] target/ppc: Correct some errors with real mode handling, David Gibson, 2020/02/18
- [PATCH v4 02/12] ppc: Remove stub of PPC970 HID4 implementation, David Gibson, 2020/02/18
- [PATCH v4 01/12] ppc: Remove stub support for 32-bit hypervisor mode, David Gibson, 2020/02/18
- [PATCH v4 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9, David Gibson, 2020/02/18
- [PATCH v4 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU, David Gibson, 2020/02/18
- [PATCH v4 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/02/18
- [PATCH v4 12/12] target/ppc: Don't store VRMA SLBE persistently, David Gibson, 2020/02/18
- [PATCH v4 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS], David Gibson, 2020/02/18
- [PATCH v4 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10, David Gibson, 2020/02/18
- [PATCH v4 09/12] target/ppc: Correct RMLS table,
David Gibson <=
- [PATCH v4 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper, David Gibson, 2020/02/18
- [PATCH v4 07/12] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/02/18
- [PATCH v4 11/12] target/ppc: Streamline construction of VRMA SLB entry, David Gibson, 2020/02/18