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[PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10
From: |
David Gibson |
Subject: |
[PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10 |
Date: |
Wed, 19 Feb 2020 11:54:08 +1100 |
Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus
from POWER7 onwards. However the translation mode which the RMOR controls
is no longer supported in POWER9, and so the register has been removed from
the architecture.
Remove it from our model on POWER9 and POWER10.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
---
target/ppc/translate_init.inc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index d7d4f012b8..c5629d8ba9 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8014,12 +8014,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_RMOR, "RMOR",
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_HRMOR, "HRMOR",
+}
+
+static void gen_spr_rmor(CPUPPCState *env)
+{
+ spr_register_hv(env, SPR_RMOR, "RMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -8534,6 +8538,7 @@ static void init_proc_POWER7(CPUPPCState *env)
/* POWER7 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_book3s_purr(env);
gen_spr_power5p_common(env);
@@ -8675,6 +8680,7 @@ static void init_proc_POWER8(CPUPPCState *env)
/* POWER8 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_iamr(env);
gen_spr_book3s_purr(env);
--
2.24.1
- Re: [PATCH v3 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper, (continued)
- [PATCH v3 02/12] ppc: Remove stub of PPC970 HID4 implementation, David Gibson, 2020/02/18
- [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode, David Gibson, 2020/02/18
- [PATCH v3 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU, David Gibson, 2020/02/18
- [PATCH v3 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS], David Gibson, 2020/02/18
- [PATCH v3 09/12] target/ppc: Correct RMLS table, David Gibson, 2020/02/18
- [PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10,
David Gibson <=
- [PATCH v3 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9, David Gibson, 2020/02/18
- [PATCH v3 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/02/18
- [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry, David Gibson, 2020/02/18
- [PATCH v3 12/12] target/ppc: Don't store VRMA SLBE persistently, David Gibson, 2020/02/18
- [PATCH v3 07/12] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/02/18
- Re: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling, no-reply, 2020/02/18
- Re: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling, David Gibson, 2020/02/18