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[PULL 24/28] ppc/pnv: Introduce a PnvCore reset handler
From: |
David Gibson |
Subject: |
[PULL 24/28] ppc/pnv: Introduce a PnvCore reset handler |
Date: |
Thu, 24 Oct 2019 19:18:09 +1100 |
From: Cédric Le Goater <address@hidden>
in which individual CPUs are reset. It will ease the introduction of
future change reseting the interrupt presenter from the CPU reset
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_core.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b1a7489e7a..9f981a4940 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -40,9 +40,8 @@ static const char *pnv_core_cpu_typename(PnvCore *pc)
return cpu_type;
}
-static void pnv_cpu_reset(void *opaque)
+static void pnv_core_cpu_reset(PowerPCCPU *cpu)
{
- PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
@@ -192,8 +191,17 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip
*chip, Error **errp)
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
+}
+
+static void pnv_core_reset(void *dev)
+{
+ CPUCore *cc = CPU_CORE(dev);
+ PnvCore *pc = PNV_CORE(dev);
+ int i;
- qemu_register_reset(pnv_cpu_reset, cpu);
+ for (i = 0; i < cc->nr_threads; i++) {
+ pnv_core_cpu_reset(pc->threads[i]);
+ }
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
@@ -244,6 +252,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
pc, name, PNV_XSCOM_EX_SIZE);
+
+ qemu_register_reset(pnv_core_reset, pc);
return;
err:
@@ -259,7 +269,6 @@ static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- qemu_unregister_reset(pnv_cpu_reset, cpu);
object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
cpu_remove_sync(CPU(cpu));
cpu->machine_data = NULL;
@@ -273,6 +282,8 @@ static void pnv_core_unrealize(DeviceState *dev, Error
**errp)
CPUCore *cc = CPU_CORE(dev);
int i;
+ qemu_unregister_reset(pnv_core_reset, pc);
+
for (i = 0; i < cc->nr_threads; i++) {
pnv_unrealize_vcpu(pc->threads[i]);
}
--
2.21.0
- [PULL 27/28] ppc/pnv: Fix naming of routines realizing the CPUs, (continued)
- [PULL 27/28] ppc/pnv: Fix naming of routines realizing the CPUs, David Gibson, 2019/10/24
- [PULL 28/28] spapr/xive: Set the OS CAM line at reset, David Gibson, 2019/10/24
- [PULL 13/28] spapr, xics, xive: Move dt_populate from SpaprIrq to SpaprInterruptController, David Gibson, 2019/10/24
- [PULL 12/28] spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptController, David Gibson, 2019/10/24
- [PULL 17/28] spapr, xics, xive: Move SpaprIrq::post_load hook to backends, David Gibson, 2019/10/24
- [PULL 06/28] spapr: Set VSMT to smp_threads by default, David Gibson, 2019/10/24
- [PULL 22/28] spapr: move CPU reset after presenter creation, David Gibson, 2019/10/24
- [PULL 15/28] spapr: Remove SpaprIrq::init_kvm hook, David Gibson, 2019/10/24
- [PULL 14/28] spapr, xics, xive: Match signatures for XICS and XIVE KVM connect routines, David Gibson, 2019/10/24
- [PULL 25/28] ppc/pnv: Add a PnvChip pointer to PnvCore, David Gibson, 2019/10/24
- [PULL 24/28] ppc/pnv: Introduce a PnvCore reset handler,
David Gibson <=
- [PULL 16/28] spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivate, David Gibson, 2019/10/24
- [PULL 26/28] ppc: Reset the interrupt presenter from the CPU reset handler, David Gibson, 2019/10/24
- [PULL 19/28] spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass, David Gibson, 2019/10/24
- [PULL 20/28] pseries: Update SLOF firmware image, David Gibson, 2019/10/24
- Re: [PULL 00/28] ppc-for-4.2 queue 20191024, Peter Maydell, 2019/10/24