Re: target/ppc: bug in optimised vsl/vsr implementation?

[Aleksandar Markovic]

> 5. (a question for Mark) After all recent changes, does get_avr64(..., ..., true) always (for any endian configuration) return the "high" half of an Altivec register, and get_avr64(..., ..., false) the "low" one?
>
> Given all these circumstances, perhaps the most reasonable solution would be to revert the commit in question, and allow Stefan enough dev and test time to hopefully submit a new, better, version later on.
>

Mark, can you verify please that this is true? The thing is, 'vsl/vsr' belong to the group of SIMD instructions where the distinction between 'high' and 'low' 64-bit halves of the source and destination registers is important (as opposed to the majority of 'regular' SIMD instructions, like vector addition, vector max/min, etc., that act only as parallel operations on corresdponding data elements).

Regards, Aleksandar

> Sincerely,
> Aleksandar
>