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[Qemu-ppc] [PULL 05/19] ppc/pnv: Introduce PowerNV machines with fixed C
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 05/19] ppc/pnv: Introduce PowerNV machines with fixed CPU models |
Date: |
Thu, 29 Aug 2019 16:08:13 +1000 |
From: Cédric Le Goater <address@hidden>
Make the current "powernv" machine an abstract type and derive from it
new machines with specific CPU models: power8 and power9.
The "powernv" machine is now an alias on the "powernv9" machine.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Adjust pnv-xscom-test to cope with this change]
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 70 +++++++++++++++++++++++++++++++++++++-----
tests/pnv-xscom-test.c | 16 ++++++++--
2 files changed, 77 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2077452d6f..3f08db7b9e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -605,9 +605,20 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip,
Monitor *mon)
pnv_psi_pic_print_info(&chip9->psi, mon);
}
+static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
+{
+ PowerPCCPUClass *ppc_default =
+ POWERPC_CPU_CLASS(object_class_by_name(default_type));
+ PowerPCCPUClass *ppc =
+ POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
+
+ return ppc_default->pvr_match(ppc_default, ppc->pvr);
+}
+
static void pnv_init(MachineState *machine)
{
PnvMachineState *pnv = PNV_MACHINE(machine);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *ram;
char *fw_filename;
long fw_size;
@@ -667,13 +678,23 @@ static void pnv_init(MachineState *machine)
}
}
+ /*
+ * Check compatibility of the specified CPU with the machine
+ * default.
+ */
+ if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
+ error_report("invalid CPU model '%s' for %s machine",
+ machine->cpu_type, mc->name);
+ exit(1);
+ }
+
/* Create the processor chips */
i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
i, machine->cpu_type);
if (!object_class_by_name(chip_typename)) {
- error_report("invalid CPU model '%.*s' for %s machine",
- i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
+ error_report("invalid chip model '%.*s' for %s machine",
+ i, machine->cpu_type, mc->name);
exit(1);
}
@@ -1351,17 +1372,38 @@ static void pnv_machine_class_props_init(ObjectClass
*oc)
NULL);
}
-static void pnv_machine_class_init(ObjectClass *oc, void *data)
+static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
+
+ mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
+
+ xic->icp_get = pnv_icp_get;
+ xic->ics_get = pnv_ics_get;
+ xic->ics_resend = pnv_ics_resend;
+}
+
+static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
+
+ mc->alias = "powernv";
+}
+
+static void pnv_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized)";
mc->init = pnv_init;
mc->reset = pnv_reset;
mc->max_cpus = MAX_CPUS;
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
* storage */
mc->no_parallel = 1;
@@ -1371,9 +1413,6 @@ static void pnv_machine_class_init(ObjectClass *oc, void
*data)
* enough to fit the maximum initrd size at it's load address
*/
mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
- xic->icp_get = pnv_icp_get;
- xic->ics_get = pnv_ics_get;
- xic->ics_resend = pnv_ics_resend;
ispc->print_info = pnv_pic_print_info;
pnv_machine_class_props_init(oc);
@@ -1393,10 +1432,27 @@ static void pnv_machine_class_init(ObjectClass *oc,
void *data)
.parent = TYPE_PNV9_CHIP, \
}
+#define DEFINE_PNV_MACHINE_TYPE(cpu, class_initfn) \
+ { \
+ .name = MACHINE_TYPE_NAME(cpu), \
+ .parent = TYPE_PNV_MACHINE, \
+ .instance_size = sizeof(PnvMachineState), \
+ .instance_init = pnv_machine_instance_init, \
+ .class_init = class_initfn, \
+ .interfaces = (InterfaceInfo[]) { \
+ { TYPE_XICS_FABRIC }, \
+ { TYPE_INTERRUPT_STATS_PROVIDER }, \
+ { }, \
+ }, \
+ }
+
static const TypeInfo types[] = {
+ DEFINE_PNV_MACHINE_TYPE("powernv8", pnv_machine_power8_class_init),
+ DEFINE_PNV_MACHINE_TYPE("powernv9", pnv_machine_power9_class_init),
{
.name = TYPE_PNV_MACHINE,
.parent = TYPE_MACHINE,
+ .abstract = true,
.instance_size = sizeof(PnvMachineState),
.instance_init = pnv_machine_instance_init,
.class_init = pnv_machine_class_init,
diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c
index 63d464048d..9fddc7d5f9 100644
--- a/tests/pnv-xscom-test.c
+++ b/tests/pnv-xscom-test.c
@@ -77,9 +77,15 @@ static void test_xscom_cfam_id(QTestState *qts, const
PnvChip *chip)
static void test_cfam_id(const void *data)
{
const PnvChip *chip = data;
+ const char *machine = "powernv8";
QTestState *qts;
- qts = qtest_initf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
+ if (chip->chip_type == PNV_CHIP_POWER9) {
+ machine = "powernv9";
+ }
+
+ qts = qtest_initf("-M %s,accel=tcg -cpu %s",
+ machine, chip->cpu_model);
test_xscom_cfam_id(qts, chip);
qtest_quit(qts);
}
@@ -113,8 +119,14 @@ static void test_core(const void *data)
{
const PnvChip *chip = data;
QTestState *qts;
+ const char *machine = "powernv8";
+
+ if (chip->chip_type == PNV_CHIP_POWER9) {
+ machine = "powernv9";
+ }
- qts = qtest_initf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
+ qts = qtest_initf("-M %s,accel=tcg -cpu %s",
+ machine, chip->cpu_model);
test_xscom_core(qts, chip);
qtest_quit(qts);
}
--
2.21.0
- [Qemu-ppc] [PULL 00/19] ppc-for-4.2 queue 20190829, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 01/19] ppc/pnv: Set default ram size to 1.75GB, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 03/19] ppc/pnv: add more dummy XSCOM addresses for the P9 CAPP, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 06/19] tests/boot-serial-test: add support for all the PowerNV machines, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 05/19] ppc/pnv: Introduce PowerNV machines with fixed CPU models,
David Gibson <=
- [Qemu-ppc] [PULL 04/19] ppc/pnv: Generate phandle for the "interrupt-parent" property, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 07/19] ppc: Fix xsmaddmdp and friends, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 11/19] target/ppc: Set float_tininess_before_rounding at cpu reset, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 10/19] pseries: Fix compat_pvr on reset, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 13/19] target/ppc: Refactor emulation of vmrgew and vmrgow instructions, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 12/19] target/ppc: Fix do_float_check_status vs inexact, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 08/19] ppc: Fix xscvdpspn for SNAN, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 18/19] spapr/pci: Convert types to QEMU coding style, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 09/19] spapr_pci: remove all child functions in function zero unplug, David Gibson, 2019/08/29
- [Qemu-ppc] [PULL 15/19] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter, David Gibson, 2019/08/29