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[Qemu-ppc] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operatio
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation |
Date: |
Sun, 30 Jun 2019 22:45:55 +0200 |
When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the
POOL interrupt context of a CPU with this special command. It returns
the POOL CAM line value and resets the VP bit.
Fixes: 4836b45510aa ("ppc/xive: activate HV support")
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/xive.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 534f56f86bd5..cf77bdb7d34a 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -132,6 +132,11 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t
ring, uint8_t cppr)
xive_tctx_notify(tctx, ring);
}
+static inline uint32_t xive_tctx_word2(uint8_t *ring)
+{
+ return *((uint32_t *) &ring[TM_WORD2]);
+}
+
/*
* XIVE Thread Interrupt Management Area (TIMA)
*/
@@ -150,11 +155,12 @@ static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr
offset, unsigned size)
static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
unsigned size)
{
- uint64_t ret;
+ uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
+ uint32_t qw2w2;
- ret = tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM;
- tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &= ~TM_QW2W2_POOL_CAM;
- return ret;
+ qw2w2 = xive_set_field32(TM_QW2W2_VP, qw2w2_prev, 0);
+ memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4);
+ return qw2w2;
}
static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
@@ -484,11 +490,6 @@ const MemoryRegionOps xive_tm_ops = {
},
};
-static inline uint32_t xive_tctx_word2(uint8_t *ring)
-{
- return *((uint32_t *) &ring[TM_WORD2]);
-}
-
static char *xive_tctx_ring_print(uint8_t *ring)
{
uint32_t w2 = xive_tctx_word2(ring);
--
2.21.0
- [Qemu-ppc] [PATCH 00/10] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 01/10] ppc/xive: Force the Physical CAM line value to group mode, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 02/10] ppc/xive: Make the PIPR register readonly, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 03/10] ppc/pnv: Rework cache watch model of PnvXIVE, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special command, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 06/10] ppc/xive: Provide escalation support, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 09/10] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 07/10] ppc/xive: Improve 'info pic' support, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 10/10] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/06/30
- [Qemu-ppc] [PATCH 08/10] ppc/xive: Extend XiveTCTX with an router object pointer, Cédric Le Goater, 2019/06/30