|
From: | G 3 |
Subject: | Re: [Qemu-ppc] [Qemu-devel] [PATCH] Implement Fraction Rounded bit in FPSCR for PowerPC |
Date: | Wed, 22 May 2019 11:25:02 -0400 |
On 5/21/19 8:06 PM, John Arbuckle wrote:
> Implement the PowerPC floating point status and control register flag Fraction Rounded.
>
> Signed-off-by: John Arbuckle <address@hidden>
> ---
> fpu/softfloat.c | 15 ++++++++++++---
> include/fpu/softfloat-types.h | 1 +
> target/ppc/fpu_helper.c | 4 ++++
> 3 files changed, 17 insertions(+), 3 deletions(-)
Please split the target/ppc part away from the softfloat part.
Also, we should note that there are more places within softfloat that need to
be adjusted so that float_float_rounded is fully supported.
r~
[Prev in Thread] | Current Thread | [Next in Thread] |