[Qemu-ppc] [PATCH 8/9] target/ppc: Fix dtstsfi and dtstsfiq

[Anton Blanchard]

The immediate field is 6 bits, not 5.

Fixes: 217f6b88058f ("target-ppc: add dtstsfi[q] instructions")
Signed-off-by: Anton Blanchard <address@hidden>
---
 target/ppc/internal.h               | 2 ++
 target/ppc/translate/dfp-impl.inc.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index fb6f64ed1e..4719369cc5 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -123,6 +123,8 @@ static inline uint32_t SPR(uint32_t opcode)
 EXTRACT_SHELPER(SIMM, 0, 16);
 /* 16 bits unsigned immediate value */
 EXTRACT_HELPER(UIMM, 0, 16);
+/* 6 bits unsigned immediate value */
+EXTRACT_HELPER(UIMM6, 16, 6);
 /* 5 bits signed immediate value */
 EXTRACT_SHELPER(SIMM5, 16, 5);
 /* 5 bits signed immediate value */
diff --git a/target/ppc/translate/dfp-impl.inc.c 
b/target/ppc/translate/dfp-impl.inc.c
index 6c556dc2e1..5b01c9239d 100644
--- a/target/ppc/translate/dfp-impl.inc.c
+++ b/target/ppc/translate/dfp-impl.inc.c
@@ -55,7 +55,7 @@ static void gen_##name(DisasContext *ctx)         \
         return;                                   \
     }                                             \
     gen_update_nip(ctx, ctx->base.pc_next - 4);            \
-    uim = tcg_const_i32(UIMM5(ctx->opcode));      \
+    uim = tcg_const_i32(UIMM6(ctx->opcode));      \
     rb = gen_fprp_ptr(rB(ctx->opcode));           \
     gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
                       cpu_env, uim, rb);          \
-- 
2.20.1