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[Qemu-ppc] [PATCH 11/14] target/ppc: decode target register in VSX_VECTO
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-ppc] [PATCH 11/14] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time |
Date: |
Sun, 28 Apr 2019 15:38:42 +0100 |
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
target/ppc/helper.h | 8 ++++----
target/ppc/mem_helper.c | 6 ++----
target/ppc/translate/vsx-impl.inc.c | 7 ++++---
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 167d6e45fd..5f844cc968 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -291,10 +291,10 @@ DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
-DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
-DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
-DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
-DEF_HELPER_4(stxvll, void, env, tl, tl, tl)
+DEF_HELPER_4(lxvl, void, env, tl, vsr, tl)
+DEF_HELPER_4(lxvll, void, env, tl, vsr, tl)
+DEF_HELPER_4(stxvl, void, env, tl, vsr, tl)
+DEF_HELPER_4(stxvll, void, env, tl, vsr, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 4dfa7ee23f..f3426315d2 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -415,9 +415,8 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#define VSX_LXVL(name, lj) \
void helper_##name(CPUPPCState *env, target_ulong addr, \
- target_ulong xt, target_ulong rb) \
+ ppc_vsr_t *r, target_ulong rb) \
{ \
- ppc_vsr_t *r = &env->vsr[xt]; \
int nb = GET_NB(env->gpr[rb]); \
int i; \
\
@@ -444,9 +443,8 @@ VSX_LXVL(lxvll, 1)
#define VSX_STXVL(name, lj) \
void helper_##name(CPUPPCState *env, target_ulong addr, \
- target_ulong xt, target_ulong rb) \
+ ppc_vsr_t *r, target_ulong rb) \
{ \
- ppc_vsr_t *r = &env->vsr[xt]; \
int nb = GET_NB(env->gpr[rb]); \
int i; \
\
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 51d4e0cdd6..7c79ec22dd 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -297,7 +297,8 @@ VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
static void gen_##name(DisasContext *ctx) \
{ \
- TCGv EA, xt, rb; \
+ TCGv EA, rb; \
+ TCGv_ptr xt; \
\
if (xT(ctx->opcode) < 32) { \
if (unlikely(!ctx->vsx_enabled)) { \
@@ -313,12 +314,12 @@ static void gen_##name(DisasContext *ctx)
\
EA = tcg_temp_new(); \
gen_set_access_type(ctx, ACCESS_INT); \
gen_addr_register(ctx, EA); \
- xt = tcg_const_tl(xT(ctx->opcode)); \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
rb = tcg_const_tl(rB(ctx->opcode)); \
gen_helper_##name(cpu_env, EA, xt, rb); \
tcg_temp_free(EA); \
- tcg_temp_free(xt); \
tcg_temp_free(rb); \
+ tcg_temp_free_ptr(xt); \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
--
2.11.0
- [Qemu-ppc] [PATCH 07/14] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c, (continued)
- [Qemu-ppc] [PATCH 07/14] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 04/14] target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 05/14] target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 01/14] target/ppc: remove getVSR()/putVSR() from fpu_helper.c, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 10/14] target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 11/14] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time,
Mark Cave-Ayland <=
- [Qemu-ppc] [PATCH 14/14] target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 12/14] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time, Mark Cave-Ayland, 2019/04/28
- [Qemu-ppc] [PATCH 13/14] target/ppc: improve VSX_TEST_DC with new generator macros, Mark Cave-Ayland, 2019/04/28