[Qemu-ppc] [PATCH 21/27] ppc/pnv: add a OCC model for POWER9

[Cédric Le Goater]

The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.

Signed-off-by: Cédric Le Goater <address@hidden>
---
 include/hw/ppc/pnv.h       |  1 +
 include/hw/ppc/pnv_occ.h   |  4 ++++
 include/hw/ppc/pnv_xscom.h |  3 +++
 hw/ppc/pnv.c               | 13 +++++++++++++
 hw/ppc/pnv_occ.c           | 40 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 61 insertions(+)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 2d68aabc212f..ad3bf0690ecf 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -86,6 +86,7 @@ typedef struct Pnv9Chip {
     PnvXive      xive;
     PnvPsi       psi;
     PnvLpcController lpc;
+    PnvOCC       occ;
 } Pnv9Chip;
 
 typedef struct PnvChipClass {
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index ce2631e21f5e..8951eb7ea316 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -27,6 +27,10 @@
 #define PNV8_OCC(obj) \
     OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC)
 
+#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
+#define PNV9_OCC(obj) \
+    OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC)
+
 typedef struct PnvOCC {
     DeviceState xd;
 
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 403a365ed274..3292459fbb78 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -73,6 +73,9 @@ typedef struct PnvXScomInterfaceClass {
 #define PNV_XSCOM_OCC_BASE        0x0066000
 #define PNV_XSCOM_OCC_SIZE        0x6000
 
+#define PNV9_XSCOM_OCC_BASE       PNV_XSCOM_OCC_BASE
+#define PNV9_XSCOM_OCC_SIZE       0x8000
+
 #define PNV9_XSCOM_PSIHB_BASE     0x5012900
 #define PNV9_XSCOM_PSIHB_SIZE     0x100
 
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 81ab53899dbc..a056064c8c11 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -968,6 +968,11 @@ static void pnv_chip_power9_instance_init(Object *obj)
                             TYPE_PNV9_LPC, &error_abort, NULL);
     object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
                                    OBJECT(&chip9->psi), &error_abort);
+
+    object_initialize_child(obj, "occ",  &chip9->occ, sizeof(chip9->occ),
+                            TYPE_PNV9_OCC, &error_abort, NULL);
+    object_property_add_const_link(OBJECT(&chip9->occ), "psi",
+                                   OBJECT(&chip9->psi), &error_abort);
 }
 
 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
@@ -1020,6 +1025,14 @@ static void pnv_chip_power9_realize(DeviceState *dev, 
Error **errp)
     }
     memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
                                 &chip9->lpc.xscom_regs);
+
+    /* Create the simplified OCC model */
+    object_property_set_bool(OBJECT(&chip9->occ), true, "realized", 
&local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+    pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
 }
 
 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index a210f44926aa..59b0702bc716 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -31,6 +31,10 @@
 #define OCB_OCI_OCCMISC_AND     0x4021
 #define OCB_OCI_OCCMISC_OR      0x4022
 
+#define P9_OCB_OCI_OCCMISC              0x6080
+#define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
+#define P9_OCB_OCI_OCCMISC_OR           0x6082
+
 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
 {
     bool irq_state;
@@ -42,6 +46,17 @@ static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
     pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
 }
 
+static void pnv_occ_p9_set_misc(PnvOCC *occ, uint64_t val)
+{
+    bool irq_state;
+
+    val &= 0xffff000000000000ull;
+
+    occ->occmisc = val;
+    irq_state = !!(val >> 63);
+    pnv_psi_irq_set(occ->psi, PSIHB9_IRQ_OCC, irq_state);
+}
+
 static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
 {
     PnvOCC *occ = PNV_OCC(opaque);
@@ -50,6 +65,7 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, 
unsigned size)
 
     switch (offset) {
     case OCB_OCI_OCCMISC:
+    case P9_OCB_OCI_OCCMISC:
         val = occ->occmisc;
         break;
     default:
@@ -75,6 +91,15 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
     case OCB_OCI_OCCMISC:
         pnv_occ_set_misc(occ, val);
         break;
+    case P9_OCB_OCI_OCCMISC_CLEAR:
+        pnv_occ_p9_set_misc(occ, 0);
+        break;
+    case P9_OCB_OCI_OCCMISC_OR:
+        pnv_occ_p9_set_misc(occ, occ->occmisc | val);
+        break;
+    case P9_OCB_OCI_OCCMISC:
+        pnv_occ_p9_set_misc(occ, val);
+       break;
     default:
         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
                       HWADDR_PRIx "\n", addr >> 3);
@@ -115,6 +140,20 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
                   occ, "xscom-occ", poc->xscom_size);
 }
 
+static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
+{
+    PnvOCCClass *poc = PNV_OCC_CLASS(klass);
+
+    poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
+}
+
+static const TypeInfo pnv_occ_power9_type_info = {
+    .name          = TYPE_PNV9_OCC,
+    .parent        = TYPE_PNV_OCC,
+    .instance_size = sizeof(PnvOCC),
+    .class_init    = pnv_occ_power9_class_init,
+};
+
 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
 {
     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
@@ -148,6 +187,7 @@ static void pnv_occ_register_types(void)
 {
     type_register_static(&pnv_occ_type_info);
     type_register_static(&pnv_occ_power8_type_info);
+    type_register_static(&pnv_occ_power9_type_info);
 }
 
 type_init(pnv_occ_register_types)
-- 
2.20.1