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[Qemu-ppc] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instruct
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instructions |
Date: |
Mon, 28 Jan 2019 10:46:15 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
When issuing a power management instruction, we set MSR:EE
to force ppc_hw_interrupt() into calling powerpc_excp()
to deal with the fact that on P7 and P8, the system reset
caused by the wakeup needs to be generated regardless of
the MSR:EE value (using LPCR only).
This however means that the OS will see a bogus SRR1:EE
value which is a problem. It also prevents properly
implementing P9 STOP "light".
So fix this by instead putting some logic in ppc_hw_interrupt()
to decide whether to deliver or not by taking into account the
fact that we are waking up from sleep.
The LPCR isn't checked as this is done in the has_work() test.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
target/ppc/excp_helper.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8407e0ade938..7c7c8d1b9dc6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -748,6 +748,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
static void ppc_hw_interrupt(CPUPPCState *env)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ bool async_deliver;
/* External reset */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
@@ -769,11 +770,20 @@ static void ppc_hw_interrupt(CPUPPCState *env)
return;
}
#endif
+
+ /*
+ * For interrupts that gate on MSR:EE, we need to do something a
+ * bit more subtle, as we need to let them through even when EE is
+ * clear when coming out of some power management states (in order
+ * for them to become a 0x100).
+ */
+ async_deliver = (msr_ee != 0) || env->in_pm_state;
+
/* Hypervisor decrementer exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
/* LPCR will be clear when not supported so this will work */
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
- if ((msr_ee != 0 || msr_hv == 0) && hdice) {
+ if ((async_deliver || msr_hv == 0) && hdice) {
/* HDEC clears on delivery */
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
@@ -783,7 +793,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
/* Extermal interrupt can ignore MSR:EE under some circumstances */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
+ if (async_deliver || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
return;
}
@@ -795,7 +805,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
return;
}
}
- if (msr_ee != 0) {
+ if (async_deliver != 0) {
/* Watchdog timer on embedded PowerPC */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
@@ -943,21 +953,14 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t
insn)
cs = CPU(ppc_env_get_cpu(env));
cs->halted = 1;
- env->in_pm_state = true;
/* The architecture specifies that HDEC interrupts are
* discarded in PM states
*/
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
- /* Technically, nap doesn't set EE, but if we don't set it
- * then ppc_hw_interrupt() won't deliver. We could add some
- * other tests there based on LPCR but it's simpler to just
- * whack EE in. It will be cleared by the 0x100 at wakeup
- * anyway. It will still be observable by the guest in SRR1
- * but this doesn't seem to be a problem.
- */
- env->msr |= (1ull << MSR_EE);
+ /* Condition for waking up at 0x100 */
+ env->in_pm_state = true;
}
#endif /* defined(TARGET_PPC64) */
--
2.20.1
- [Qemu-ppc] [PATCH 08/19] target/ppc: Fix nip on power management instructions, (continued)
- [Qemu-ppc] [PATCH 08/19] target/ppc: Fix nip on power management instructions, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 05/19] ppc/pnv: add XIVE support, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 13/19] target/ppc: Rename "in_pm_state" to "resume_as_sreset", Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 14/19] target/ppc: Add POWER9 exception model, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 17/19] target/ppc: Add POWER9 external interrupt model, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 16/19] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 11/19] target/ppc: Move "wakeup reset" code to a separate function, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 12/19] target/ppc: Disable ISA 2.06 PM instructions on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instructions,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interrupt types, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 15/19] target/ppc: Detect erroneous condition in interrupt delivery, Cédric Le Goater, 2019/01/28