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[Qemu-ppc] [PATCH 00/19] ppc: support for the baremetal XIVE interrupt c

From: Cédric Le Goater
Subject: [Qemu-ppc] [PATCH 00/19] ppc: support for the baremetal XIVE interrupt controller (POWER9)
Date: Mon, 28 Jan 2019 10:46:06 +0100


Here is a series adding support for the XIVE interrupt controller as
found on POWER9 PowerNV mchines. It includes models for the baremetal
IC itself and a set of fixes and extensions of the POWER9 core
provided by Ben.



Changes in v1 (since PnvXive was last sent) :

 - made more use of the register values instead of caching them under
 - generalized the VST accessors.
 - reworked indirect accesses to the TIMA with a custom get_tctx()
 - fixed the translation table definitions
 - XiveSource and XiveENDSource objects are now sized to the maximum
   allowed by HW and the memory regions exposing the ESB pages are
   resized at runtime when the firmware configures the controller.
 - included changes from Ben on the POWER9 core model to fix power
   management instructions, add support for sreset and the HV
   interrupt line

Benjamin Herrenschmidt (14):
  target/ppc: Remove some #if 0'ed code
  target/ppc: Make special ORs match x86 pause and don't generate on
  target/ppc: Fix nip on power management instructions
  target/ppc: Don't clobber MSR:EE on PM instructions
  target/ppc: Fix support for "STOP light" states on POWER9
  target/ppc: Move "wakeup reset" code to a separate function
  target/ppc: Disable ISA 2.06 PM instructions on POWER9
  target/ppc: Rename "in_pm_state" to "resume_as_sreset"
  target/ppc: Add POWER9 exception model
  target/ppc: Detect erroneous condition in interrupt delivery
  target/ppc: Add Hypervisor Virtualization Interrupt on POWER9
  target/ppc: Add POWER9 external interrupt model
  ppc/xive: Make XIVE generate the proper interrupt types
  target/ppc: Add support for LPCR:HEIC on POWER9

Cédric Le Goater (5):
  ppc/xive: hardwire the Physical CAM line of the thread context
  ppc: externalize ppc_get_vcpu_by_pir()
  xive: extend the XiveRouter get_tctx() method with the page offset
  ppc/pnv: xive: export the TIMA memory accessors
  ppc/pnv: add XIVE support

 hw/intc/pnv_xive_regs.h         |  315 ++++++
 include/hw/ppc/pnv.h            |   21 +
 include/hw/ppc/pnv_core.h       |    1 +
 include/hw/ppc/pnv_xive.h       |   95 ++
 include/hw/ppc/pnv_xscom.h      |    3 +
 include/hw/ppc/ppc.h            |    3 +
 include/hw/ppc/xive.h           |   12 +-
 target/ppc/cpu-qom.h            |    5 +
 target/ppc/cpu.h                |   26 +-
 hw/intc/pnv_xive.c              | 1698 +++++++++++++++++++++++++++++++
 hw/intc/spapr_xive.c            |    3 +-
 hw/intc/xics.c                  |    1 +
 hw/intc/xive.c                  |  167 ++-
 hw/ppc/pnv.c                    |   84 +-
 hw/ppc/pnv_core.c               |   16 +-
 hw/ppc/ppc.c                    |   32 +-
 target/ppc/excp_helper.c        |  176 ++--
 target/ppc/mmu_helper.c         |   12 -
 target/ppc/translate.c          |   34 +-
 target/ppc/translate_init.inc.c |   36 +-
 hw/intc/Makefile.objs           |    2 +-
 21 files changed, 2593 insertions(+), 149 deletions(-)
 create mode 100644 hw/intc/pnv_xive_regs.h
 create mode 100644 include/hw/ppc/pnv_xive.h
 create mode 100644 hw/intc/pnv_xive.c


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