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Re: [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations |
Date: |
Wed, 19 Dec 2018 17:32:33 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:38:58PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> ---
> target/ppc/translate/vmx-impl.inc.c | 26 +++-----------------------
> 1 file changed, 3 insertions(+), 23 deletions(-)
>
> diff --git a/target/ppc/translate/vmx-impl.inc.c
> b/target/ppc/translate/vmx-impl.inc.c
> index 529ae0e5f5..329131d30b 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -277,34 +277,14 @@ static void glue(gen_, name)(DisasContext *ctx)
> \
> 16, 16); \
> }
>
> -#define GEN_VXFORM_VN(name, vece, tcg_op, opc2, opc3) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - if (unlikely(!ctx->altivec_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_VPU); \
> - return; \
> - } \
> - \
> - tcg_op(vece, \
> - avr64_offset(rD(ctx->opcode), true), \
> - avr64_offset(rA(ctx->opcode), true), \
> - avr64_offset(rB(ctx->opcode), true), \
> - 16, 16); \
> - \
> - tcg_gen_gvec_not(vece, \
> - avr64_offset(rD(ctx->opcode), true), \
> - avr64_offset(rD(ctx->opcode), true), \
> - 16, 16); \
> -}
> -
> /* Logical operations */
> GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
> GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
> GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
> GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
> -GEN_VXFORM_VN(vnor, MO_64, tcg_gen_gvec_or, 2, 20);
> -GEN_VXFORM_VN(veqv, MO_64, tcg_gen_gvec_xor, 2, 26);
> -GEN_VXFORM_VN(vnand, MO_64, tcg_gen_gvec_and, 2, 22);
> +GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
> +GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
> +GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
> GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
>
> #define GEN_VXFORM(name, opc2, opc3) \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate, (continued)
- [Qemu-ppc] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 31/34] target/ppc: Add set_vscr_sat, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations, Richard Henderson, 2018/12/18
- Re: [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations,
David Gibson <=
- [Qemu-ppc] [PATCH 04/34] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 29/34] target/ppc: Add helper_mfvscr, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18