[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] Missing POWER9 addex

From: Suraj Jitindar Singh
Subject: Re: [Qemu-ppc] Missing POWER9 addex
Date: Wed, 14 Nov 2018 14:22:03 +1100

On Sun, 2018-11-11 at 15:36 +0100, Torbjörn Granlund wrote:
> The addex instruction seems to be missing from qemu, even from the
> 3.1
> snapshots.

To be clear, you're asking for support for the addex instruction to be
added to qemu tcg for powerpc?

> We use this instruction in the latest GMP snapshots, leading to illop
> signals.
> This is an instruction added to P9.  It is akin to adde but uses the
> OV
> bit for carry in/out instead of the CA bit.
> Please note that there is a slight oddity with this instruction's
> coding.  The secondary opcode is 170, but it is documented as coded
> in
> bits 23 through 30.  Other arithmetic insns' secondary opcode is
> placed
> in bits 22 through 30.
> It might be neater to treat addex like other arithmetic insns, and
> put
> the opcode 170 in bits 22..30.  That would make bit 22 zero, but
> since
> the CY field in bits 21..22 needs to be 00 currently (other values
> are
> reserved) this should not matter.

reply via email to

[Prev in Thread] Current Thread [Next in Thread]