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[Qemu-ppc] [PULL 12/22] target/ppc: Split out float_invalid_cvt
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From: |
David Gibson |
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Subject: |
[Qemu-ppc] [PULL 12/22] target/ppc: Split out float_invalid_cvt |
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Date: |
Thu, 8 Nov 2018 23:16:36 +1100 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 67 +++++++++++++++++------------------------
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 127c08bcec..2ed4f42275 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -750,30 +750,30 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1,
float64 arg2)
return ret;
}
+static void float_invalid_cvt(CPUPPCState *env, bool set_fprc,
+ uintptr_t retaddr, int class1)
+{
+ float_invalid_op_vxcvi(env, set_fprc, retaddr);
+ if (class1 & is_snan) {
+ float_invalid_op_vxsnan(env, retaddr);
+ }
+}
#define FPU_FCTI(op, cvt, nanval) \
-uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
+uint64_t helper_##op(CPUPPCState *env, float64 arg) \
{ \
- CPU_DoubleU farg; \
- \
- farg.ll = arg; \
- farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
+ uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
+ int status = get_float_exception_flags(&env->fp_status); \
\
- if (unlikely(env->fp_status.float_exception_flags)) { \
- if (float64_is_any_nan(arg)) { \
- float_invalid_op_vxcvi(env, 1, GETPC()); \
- if (float64_is_signaling_nan(arg, &env->fp_status)) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
- farg.ll = nanval; \
- } else if (env->fp_status.float_exception_flags & \
- float_flag_invalid) { \
- float_invalid_op_vxcvi(env, 1, GETPC()); \
+ if (unlikely(status)) { \
+ if (status & float_flag_invalid) { \
+ float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
+ ret = nanval; \
} \
do_float_check_status(env, GETPC()); \
} \
- return farg.ll; \
- }
+ return ret; \
+}
FPU_FCTI(fctiw, int32, 0x80000000U)
FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
@@ -2965,6 +2965,7 @@ uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
+ int all_flags = env->fp_status.float_exception_flags, flags; \
ppc_vsr_t xt, xb; \
int i; \
\
@@ -2972,22 +2973,18 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
getVSR(xT(opcode), &xt, env); \
\
for (i = 0; i < nels; i++) { \
- if (unlikely(stp##_is_any_nan(xb.sfld))) { \
- if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
- float_invalid_op_vxcvi(env, 0, GETPC()); \
+ env->fp_status.float_exception_flags = 0; \
+ xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); \
+ flags = env->fp_status.float_exception_flags; \
+ if (unlikely(flags & float_flag_invalid)) { \
+ float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); \
xt.tfld = rnan; \
- } else { \
- xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
- &env->fp_status); \
- if (env->fp_status.float_exception_flags & float_flag_invalid) { \
- float_invalid_op_vxcvi(env, 0, GETPC()); \
- } \
} \
+ all_flags |= flags; \
} \
\
putVSR(xT(opcode), &xt, env); \
+ env->fp_status.float_exception_flags = all_flags; \
do_float_check_status(env, GETPC()); \
}
@@ -3025,18 +3022,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
getVSR(rB(opcode) + 32, &xb, env); \
memset(&xt, 0, sizeof(xt)); \
\
- if (unlikely(stp##_is_any_nan(xb.sfld))) { \
- if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
- float_invalid_op_vxcvi(env, 0, GETPC()); \
+ xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); \
+ if (env->fp_status.float_exception_flags & float_flag_invalid) { \
+ float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); \
xt.tfld = rnan; \
- } else { \
- xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
- &env->fp_status); \
- if (env->fp_status.float_exception_flags & float_flag_invalid) { \
- float_invalid_op_vxcvi(env, 0, GETPC()); \
- } \
} \
\
putVSR(rD(opcode) + 32, &xt, env); \
--
2.19.1
- [Qemu-ppc] [PULL 04/22] PPC: e500: convert SysBus init method to a realize method, (continued)
- [Qemu-ppc] [PULL 04/22] PPC: e500: convert SysBus init method to a realize method, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 11/22] target/ppc: Split out float_invalid_op_div, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 19/22] hw/ppc/ppc440_uc: Remove dead code in sdram_size(), David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 13/22] spapr_pci: convert g_malloc() to g_new(), David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 09/22] target/ppc: Split out float_invalid_op_addsub, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 20/22] This patch fixes processing of rfi instructions in icount mode., David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 05/22] hw/ppc/spapr_rng: Introduce CONFIG_SPAPR_RNG switch for spapr_rng.c, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 18/22] MAINTAINERS: PPC: Remove myself, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 22/22] ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 12/22] target/ppc: Split out float_invalid_cvt,
David Gibson <=
- [Qemu-ppc] [PULL 06/22] target/ppc: Split up float_invalid_op_excp, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 01/22] target/ppc: add external PID support, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 07/22] target/ppc: Remove float_check_status, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 15/22] hw/ppc/mac_newworld: Free openpic_irqs array after use, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 14/22] macio/pmu: Fix missing vmsd terminator, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 16/22] target/ppc: fix mtmsr instruction for icount, David Gibson, 2018/11/08
- [Qemu-ppc] [PULL 21/22] target/ppc: Add one reg id for ptcr, David Gibson, 2018/11/08