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Re: [Qemu-ppc] [Qemu-devel] Help with softfloat.c code
From: |
Programmingkid |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] Help with softfloat.c code |
Date: |
Mon, 17 Sep 2018 21:59:38 -0400 |
> On Sep 17, 2018, at 2:51 PM, Peter Maydell <address@hidden> wrote:
>
> On 17 September 2018 at 18:56, Programmingkid <address@hidden> wrote:
>>
>>> On Sep 17, 2018, at 1:52 PM, Peter Maydell <address@hidden> wrote:
>>>
>>> On 17 September 2018 at 18:48, Programmingkid <address@hidden> wrote:
>>>> What I hope to do is implement a PowerPC CPU flag that indicates if an
>>>> rounded result is inexact.
>>>
>>> How is this different from the float_flag_inexact flag that softfloat
>>> already
>>> supports ?
>>
>> Sorry I meant to say if a rounded result is different from the intermediate
>> result. This is what the FPSCR[FR] flag indicates on the PowerPC.
>
> Looking at the PPC spec that seems to be "inexact but not overflow" so you
> should be able to calculate it via suitable handling of our existing
> float flags.
So if an inexact exception takes place without the overflow bit set, it means
the fraction rounded bit should be set? I don't believe that would work for
PowerPC.