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[Qemu-ppc] [PULL 24/33] target/ppc: Allow PIR read in privileged mode
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 24/33] target/ppc: Allow PIR read in privileged mode |
Date: |
Tue, 12 Jun 2018 16:44:54 +1000 |
From: luporl <address@hidden>
According to PowerISA, the PIR register should be readable in privileged
mode also, not only in hypervisor privileged mode.
PowerISA 3.0 - 4.3.3 Processor Identification Register
"Read access to the PIR is privileged; write access is not provided."
Figure 18 in section 4.4.4 explicitly confirms that mfspr PIR is privileged
and doesn't require hypervisor state.
Cc: David Gibson <address@hidden>
Cc: Alexander Graf <address@hidden>
Cc: address@hidden
Signed-off-by: Leandro Lupori <address@hidden>
Reviewed-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate_init.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 1a89017dde..bb9296f5a3 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -7819,7 +7819,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
/* Processor identification */
spr_register_hv(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
&spr_read_generic, NULL,
0x00000000);
spr_register_hv(env, SPR_HID0, "HID0",
--
2.17.1
- [Qemu-ppc] [PULL 12/33] MAINTAINERS: Add an entry for the MacIO device headers, (continued)
- [Qemu-ppc] [PULL 12/33] MAINTAINERS: Add an entry for the MacIO device headers, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 19/33] cuda: embed mos6522_cuda device directly rather than using QOM object link, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 22/33] target/ppc: extend eieio for POWER9, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 18/33] mos6522: fix vmstate_mos6522_timer version in vmstate_mos6522, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 29/33] spapr: handle pc-dimm unplug via hotplug handler chain, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 30/33] spapr: handle cpu core unplug via hotplug handler chain, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 31/33] ppc/pnv: fix LPC HC firmware address space, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 21/33] mos6522: convert VMSTATE_TIMER_PTR_TEST to VMSTATE_TIMER_PTR, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 26/33] spapr: move lookup of the node into spapr_memory_plug(), David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 33/33] spapr_pci: Remove unhelpful pagesize warning, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 24/33] target/ppc: Allow PIR read in privileged mode,
David Gibson <=
- [Qemu-ppc] [PULL 25/33] spapr: no need to verify the node, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 23/33] ppc4xx_i2c: Clean up and improve error logging, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 32/33] xics_kvm: use KVM helpers, David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 27/33] spapr: move memory hotplug support check into spapr_memory_pre_plug(), David Gibson, 2018/06/12
- [Qemu-ppc] [PULL 28/33] spapr: introduce machine unplug handler, David Gibson, 2018/06/12
- Re: [Qemu-ppc] [PULL 00/33] ppc-for-3.0 queue 20180612, Peter Maydell, 2018/06/12