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Re: [Qemu-ppc] [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in pri


From: Greg Kurz
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode
Date: Tue, 5 Jun 2018 18:46:12 +0200

On Mon, 4 Jun 2018 10:53:22 +1000
David Gibson <address@hidden> wrote:

> On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote:
> > According to PowerISA, the PIR register should be readable in privileged
> > mode also, not only in hypervisor privileged mode.
> > 
> > PowerISA 3.0 - 4.3.3 Processor Identification Register
> > 
> > "Read access to the PIR is privileged; write access is not
> > provided."  
> 
> Yes... but a little further down it says "The PIR is a hypervisor
> resource".  Looking at the older 2.07 ISA, it says that
> guest-supervisor mode reads to the PIR should be redirected to the
> GPIR register, which this change won't accomplish.
> 

Hmmm, there are two definitions for the PIR, one in Book III-S (4.3.3)
and one in Book III-E (5.3.3). It looks like you're referring to the
latter...

[Category:Embedded.Hypervisor]
Read accesses to the PIR in guest supervisor state are
mapped to the GPIR.

The Book III-S definition doesn't mention the GPIR.

> So, I'm not sure what to make of this.
> 
> > 
> > Cc: David Gibson <address@hidden>
> > Cc: Alexander Graf <address@hidden>
> > Cc: address@hidden
> > Signed-off-by: Leandro Lupori <address@hidden>
> > Reviewed-by: Jose Ricardo Ziviani <address@hidden>
> > Reviewed-by: Greg Kurz <address@hidden>
> > ---
> > Changes in v2:
> > - added my Signed-off-by, maintainers CC and Jose's Reviewed-by tags
> > 
> > Changes in v3:
> > - added subsystem name, version tag and summary of changes
> > - added the section of PowerISA that describes PIR access privileges
> > 
> >  target/ppc/translate_init.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > index a72be6d121..7b56e3ffb9 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -7816,7 +7816,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> >      /* Processor identification */
> >      spr_register_hv(env, SPR_PIR, "PIR",
> >                   SPR_NOACCESS, SPR_NOACCESS,
> > -                 SPR_NOACCESS, SPR_NOACCESS,
> > +                 &spr_read_generic, SPR_NOACCESS,
> >                   &spr_read_generic, NULL,
> >                   0x00000000);
> >      spr_register_hv(env, SPR_HID0, "HID0",  
> 

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