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[Qemu-ppc] [PATCH v2 07/19] spapr: push the XIVE EQ data in OS event que
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v2 07/19] spapr: push the XIVE EQ data in OS event queue |
Date: |
Sat, 9 Dec 2017 09:43:26 +0100 |
If a triggered event is let through by the XIVE virtualization routing
engine, the Event Queue data defined in the associated IVE is pushed
in the in-memory event queue. The latter is a circular buffer provided
by the OS using the H_INT_SET_QUEUE_CONFIG hcall, one per server and
priority couple. Each Event Queue entry is 4 bytes long, the first bit
being a 'generation' bit and the 31 following bits the EQ Data field.
The EQ Data field provides a way to set an invariant logical event
source number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG
hcall when the EISN flag is used.
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v1:
- replaced dma_memory_write() by stl_be_dma()
- improved 'info pic' output
hw/intc/spapr_xive.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 8e990d58ecf4..629563d01998 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -196,9 +196,87 @@ static sPAPRXiveNVT *spapr_xive_nvt_get(sPAPRXive *xive,
int server)
return cpu ? SPAPR_XIVE_NVT(cpu->intc) : NULL;
}
+static void spapr_xive_pic_print_info_eq(XiveEQ *eq, Monitor *mon)
+{
+ uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;
+ uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);
+ uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);
+ uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);
+ uint32_t qentries = 1 << (qsize + 10);
+
+ monitor_printf(mon, "eq:@%08" PRIx64"% 6d/%5d ^%d", qaddr_base,
+ qindex, qentries, qgen);
+}
+
+static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)
+{
+ uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;
+ uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);
+ uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);
+ uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);
+
+ uint64_t qaddr = qaddr_base + (qindex << 2);
+ uint32_t qdata = (qgen << 31) | (data & 0x7fffffff);
+ uint32_t qentries = 1 << (qsize + 10);
+
+ if (stl_be_dma(&address_space_memory, qaddr, qdata)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write EQ data @0x%"
+ HWADDR_PRIx "\n", qaddr);
+ return;
+ }
+
+ qindex = (qindex + 1) % qentries;
+ if (qindex == 0) {
+ qgen ^= 1;
+ eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);
+ }
+ eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);
+}
+
static void spapr_xive_irq(sPAPRXive *xive, int lisn)
{
+ XiveIVE *ive;
+ XiveEQ *eq;
+ uint32_t eq_idx;
+ uint8_t priority;
+
+ ive = spapr_xive_get_ive(xive, lisn);
+ if (!ive || !(ive->w & IVE_VALID)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %d\n", lisn);
+ return;
+ }
+ if (ive->w & IVE_MASKED) {
+ return;
+ }
+
+ /* Find our XiveEQ */
+ eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);
+ eq = spapr_xive_get_eq(xive, XIVE_EQ_INDEX_SERVER(eq_idx),
+ XIVE_EQ_INDEX_PRIO(eq_idx));
+ if (!eq) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No EQ for LISN %d\n", lisn);
+ return;
+ }
+
+ if (eq->w0 & EQ_W0_ENQUEUE) {
+ spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));
+ }
+
+ if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {
+ qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n");
+ }
+
+ if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {
+ priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);
+
+ /* The EQ is masked. Can this happen ? */
+ if (priority == 0xff) {
+ g_assert_not_reached();
+ }
+ } else {
+ qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n");
+ }
}
/*
@@ -480,14 +558,28 @@ void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor
*mon)
pq = spapr_xive_pq_get(xive, i);
eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);
- monitor_printf(mon, " %4x %s %s %c%c server:%d prio:%d %08x\n", i,
+ monitor_printf(mon, " %4x %s %s %c%c server:%d prio:%d ", i,
spapr_xive_irq_is_lsi(xive, i) ? "LSI" : "MSI",
ive->w & IVE_MASKED ? "M" : " ",
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
XIVE_EQ_INDEX_SERVER(eq_idx),
- XIVE_EQ_INDEX_PRIO(eq_idx),
- (int) GETFIELD(IVE_EQ_DATA, ive->w));
+ XIVE_EQ_INDEX_PRIO(eq_idx));
+
+ if (!(ive->w & IVE_MASKED)) {
+ XiveEQ *eq;
+
+ eq = spapr_xive_get_eq(xive, XIVE_EQ_INDEX_SERVER(eq_idx),
+ XIVE_EQ_INDEX_PRIO(eq_idx));
+ if (eq) {
+ spapr_xive_pic_print_info_eq(eq, mon);
+ monitor_printf(mon, " data:%08x",
+ (int) GETFIELD(IVE_EQ_DATA, ive->w));
+ } else {
+ monitor_printf(mon, "no eq ?!");
+ }
+ }
+ monitor_printf(mon, "\n");
}
}
--
2.13.6
- Re: [Qemu-ppc] [PATCH v2 03/19] spapr: introduce the XIVE interrupt sources, (continued)
Re: [Qemu-ppc] [PATCH v2 03/19] spapr: introduce the XIVE interrupt sources, David Gibson, 2017/12/20
[Qemu-ppc] [PATCH v2 04/19] spapr: add support for the LSI interrupt sources, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 05/19] spapr: introduce a XIVE interrupt presenter model, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 06/19] spapr: introduce the XIVE Event Queues, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 07/19] spapr: push the XIVE EQ data in OS event queue,
Cédric Le Goater <=
[Qemu-ppc] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrupt priority is more privileged, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 09/19] spapr: add support for the SET_OS_PENDING command (XIVE), Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 10/19] spapr: introduce a 'xive_exploitation' boolean to enable XIVE, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 11/19] spapr: add a sPAPRXive object to the machine, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 12/19] spapr: add hcalls support for the XIVE exploitation interrupt mode, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 13/19] spapr: add device tree support for the XIVE interrupt mode, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 14/19] spapr: introduce a helper to map the XIVE memory regions, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 15/19] spapr: add XIVE support to spapr_qirq(), Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 16/19] spapr: introduce a spapr_icp_create() helper, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 17/19] spapr: toggle the ICP depending on the selected interrupt mode, Cédric Le Goater, 2017/12/09