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[Qemu-ppc] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TC
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest |
Date: |
Thu, 11 May 2017 14:14:21 +1000 |
From: Suraj Jitindar Singh <address@hidden>
Now that we have added all the infrastructure we can enable a pseries TCG
guest to use radix.
In order to do this we have to add the appropriate bits to the
ibm,arch-vec-5-platform-support vector to represent that we support both
hash and radix mmu models.
A radix guest can now be booted in pseries tcg mode by specifying:
-cpu POWER9
Note that we assume hash, that is we allocate a hpt, until a guest tells
us otherwise via a H_REGISTER_PROCESS_TABLE call with radix specified - in
which case we free the hpt. If we were right and the guest is hash then
there's nothing for us to do.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 80d12d0..e2dc77c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -855,6 +855,8 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void
*fdt)
* option vector 5: */
static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
{
+ PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+
char val[2 * 3] = {
24, 0x00, /* Hash/Radix, filled in below. */
25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
@@ -870,8 +872,13 @@ static void spapr_dt_ov5_platform_support(void *fdt, int
chosen)
val[1] = 0x00; /* Hash */
}
} else {
- /* TODO: TCG case, hash */
- val[1] = 0x00;
+ if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {
+ /* V3 MMU supports both hash and radix (with dynamic switching) */
+ val[1] = 0xC0;
+ } else {
+ /* Otherwise we can only do hash */
+ val[1] = 0x00;
+ }
}
_FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
val, sizeof(val)));
@@ -2101,8 +2108,8 @@ static void ppc_spapr_init(MachineState *machine)
}
spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
- if (kvmppc_has_cap_mmu_radix()) {
- /* KVM always allows GTSE with radix... */
+ if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
+ /* KVM and TCG always allow GTSE with radix... */
spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
}
/* ... but not with hash (currently). */
--
2.9.3
- [Qemu-ppc] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers, (continued)
- [Qemu-ppc] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 19/23] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 05/23] cpus: Fix CPU unplug for MTTCG, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 10/23] Add QemuMacDrivers as submodule, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 21/23] target/ppc: Allow workarounds for POWER9 DD1, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest,
David Gibson <=
- [Qemu-ppc] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 14/23] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 17/23] target/ppc: Implement ISA V3.00 radix page fault handler, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 16/23] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 20/23] spapr: Don't accidentally advertise HTM support on POWER9, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 22/23] pnv: Fix build failures on some host platforms, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 23/23] target/ppc: Avoid printing wrong aliases in CPU help text, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 11/23] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built as submodule, David Gibson, 2017/05/11