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Re: [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbi


From: David Gibson
Subject: Re: [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbie to check privilege level based on GTSE
Date: Tue, 2 May 2017 11:46:07 +1000
User-agent: Mutt/1.8.0 (2017-02-23)

On Fri, Apr 28, 2017 at 04:58:23PM +1000, Suraj Jitindar Singh wrote:
> The Guest Translation Shootdown Enable (GTSE) bit in the Logical Partition
> Control Register (LPCR) can be set to enable a guest to use the tlbie
> instruction directly to invalidate translations.
> 
> When the GTSE bit is set then the tlbie instruction is supervisor
> privileged, otherwise it is hypervisor privileged.
> 
> Add a guest translation shootdown enable (gtse) field to the diassembly
> context and use this to check the correct privilege level at code
> generation time.
> 
> Signed-off-by: Suraj Jitindar Singh <address@hidden>

Reviewed-by: David Gibson <address@hidden>

> 
> ---
> 
> V4 -> V5:
> - Add to and use a field in the DisasContext so that we check at code gen
>   time rather than execution time
> 
> -> V4:
> - Added patch to series
> ---
>  target/ppc/translate.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f40b5a1..e8aa83d 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -214,6 +214,7 @@ struct DisasContext {
>      bool vsx_enabled;
>      bool spe_enabled;
>      bool tm_enabled;
> +    bool gtse;
>      ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
>      int singlestep_enabled;
>      uint64_t insns_flags;
> @@ -4513,7 +4514,12 @@ static void gen_tlbie(DisasContext *ctx)
>      GEN_PRIV;
>  #else
>      TCGv_i32 t1;
> -    CHK_HV;
> +
> +    if (ctx->gtse) {
> +        CHK_SV; /* If gtse is set then tblie is supervisor privileged */
> +    } else {
> +        CHK_HV; /* Else hypervisor privileged */
> +    }
>  
>      if (NARROW_MODE(ctx)) {
>          TCGv t0 = tcg_temp_new();
> @@ -7227,6 +7233,7 @@ void gen_intermediate_code(CPUPPCState *env, struct 
> TranslationBlock *tb)
>          ctx.tm_enabled = false;
>      }
>  #endif
> +    ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
>      if ((env->flags & POWERPC_FLAG_SE) && msr_se)
>          ctx.singlestep_enabled = CPU_SINGLE_STEP;
>      else

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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