[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POW
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POWER9 |
Date: |
Wed, 1 Mar 2017 17:54:34 +1100 |
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Balbir Singh <address@hidden>
---
V4 -> V5:
- Nothing
V3 -> V4:
- Add define for LPCR_HR - Host Radix bit. Note this bit not used yet
- Use if instead of switch for V3 mmu model
---
target/ppc/cpu.h | 20 ++++++++++++++++++++
target/ppc/mmu-hash64.c | 8 ++++++++
target/ppc/translate_init.c | 22 ++++++++++++++++------
3 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8c849cb..9e7b27c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -377,12 +377,21 @@ struct ppc_slb_t {
#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
#define LPCR_VRMASD_SHIFT (63 - 16)
#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
+/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
+#define LPCR_PECE_U_SHIFT (63 - 19)
+#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
+#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
#define LPCR_RMLS_SHIFT (63 - 37)
#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
#define LPCR_ILE (1ull << (63 - 38))
#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
+#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */
+#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */
+/* Host Radix - Mirrors the HR bit in the Partition Table */
+#define LPCR_HR (1ull << (63 - 43))
#define LPCR_ONL (1ull << (63 - 45))
+#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */
#define LPCR_P7_PECE0 (1ull << (63 - 49))
#define LPCR_P7_PECE1 (1ull << (63 - 50))
#define LPCR_P7_PECE2 (1ull << (63 - 51))
@@ -391,11 +400,22 @@ struct ppc_slb_t {
#define LPCR_P8_PECE2 (1ull << (63 - 49))
#define LPCR_P8_PECE3 (1ull << (63 - 50))
#define LPCR_P8_PECE4 (1ull << (63 - 51))
+/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
+#define LPCR_PECE_L_SHIFT (63 - 51)
+#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
+#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
+#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
+#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */
+#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */
+#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */
#define LPCR_MER (1ull << (63 - 52))
+#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */
#define LPCR_TC (1ull << (63 - 54))
+#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */
#define LPCR_LPES0 (1ull << (63 - 60))
#define LPCR_LPES1 (1ull << (63 - 61))
#define LPCR_RMI (1ull << (63 - 62))
+#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable
*/
#define LPCR_HDICE (1ull << (63 - 63))
#define msr_sf ((env->msr >> MSR_SF) & 1)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index f2e619e..6261bac 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1009,6 +1009,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong
val)
LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
break;
+ case POWERPC_MMU_3_00: /* P9 */
+ lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
+ break;
default:
;
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index c95c9cd..a6e56ec 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8878,12 +8878,22 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
PPCVirtualHypervisor *vhyp)
lpcr->default_value &= ~LPCR_RMLS;
lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
- /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
- * bit 47 and 48 which are reserved on P7. Here we set them all, which
- * will work as expected for both implementations
- */
- lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ /* By default we choose legacy mode and switch to new hash or radix
+ * when a register process table hcall is made. So disable process
+ * tables and guest translation shootdown by default
+ */
+ lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
+ lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
+ LPCR_OEE;
+ } else {
+ /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
+ * bit 47 and 48 which are reserved on P7. Here we set them all, which
+ * will work as expected for both implementations
+ */
+ lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
+ }
/* We should be followed by a CPU reset but update the active value
* just in case...
--
2.5.5
- [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POWER9,
Suraj Jitindar Singh <=
- [Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 4/9] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 6/9] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 5/9] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 8/9] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 9/9] hw/ppc/spapr: Add POWER9 to pseries cpu models, Suraj Jitindar Singh, 2017/03/01
- Re: [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, David Gibson, 2017/03/01