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Re: [Qemu-ppc] [QEMU-PPC] [PATCH V4 01/11] target/ppc/POWER9: Add ISAv3.
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From: |
Balbir Singh |
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Subject: |
Re: [Qemu-ppc] [QEMU-PPC] [PATCH V4 01/11] target/ppc/POWER9: Add ISAv3.00 MMU definition |
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Date: |
Mon, 27 Feb 2017 11:43:57 +1100 |
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User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Fri, Feb 24, 2017 at 12:05:07PM +1100, Suraj Jitindar Singh wrote:
> POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
>
> Add a definition for this mmu model and set the POWER9 cpu model to use
> this mmu model.
>
> Signed-off-by: Suraj Jitindar Singh <address@hidden>
>
> ---
>
> V3 -> V4:
> - Add POWERPC_MMU_V3 flag to mmu model
> ---
Acked-by: Balbir Singh <address@hidden>
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 00/11] target/ppc: Implement POWER9 pseries tcg legacy support, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 01/11] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 02/11] target/ppc: Fix LPCR DPFD mask define, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 03/11] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 04/11] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 06/11] target/ppc: Remove the function ppc_hash64_set_sdr1(), Suraj Jitindar Singh, 2017/02/23