Re: [Qemu-ppc] [Qemu-devel] [RFC PATCH v0] softfloat: Add round-to-odd rounding mode

[Eric Blake]

On 01/18/2017 11:14 PM, Bharata B Rao wrote:
> Power ISA 3.0 introduces a few quadruple precision floating point
> instructions that support round-to-add rounding mode. The

s/add/odd/

> round-to-odd mode is explained as under:
> 
> Let Z be the intermediate arithmetic result or the operand of a convert
> operation. If Z can be represented exactly in the target format, the
> result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
> Here Z1 and Z2 are the next larger and smaller numbers representable
> in the target format respectively.

IEEE 854 and thus POSIX <float.h> specifies round-to-zero,
round-to-pos-inf, round-to-neg-inf, and round-to-even. It sounds like
round-to-odd is similar to round-to-even, only that the ties are broken
in the opposite direction.  I don't know if portable C code can even
request this mode (although float.h is allowed to add additional
implementation-defined values to FLT_ROUNDS), but since the hardware can
do it, I guess we have to emulate it.

> 
> Signed-off-by: Bharata B Rao <address@hidden>
> ---
> - I am not fully sure if this the correct implementation for the above
>   described round-to-odd rounding method. Any help is appreciated.

I don't know the code either, but if round-to-even is implemented
correctly, it sounds like round-to-odd is a one-off tweak from that.


-- 
Eric Blake   eblake redhat com    +1-919-301-3266
Libvirt virtualization library http://libvirt.org

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