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[Qemu-ppc] [PATCH 13/14] target-ppc: Add xsxsigdp instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH 13/14] target-ppc: Add xsxsigdp instruction |
Date: |
Thu, 5 Jan 2017 16:56:18 +0530 |
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 514a273..1fea8dc 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -1242,6 +1242,35 @@ static void gen_xsxexpqp(DisasContext *ctx)
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_movi_i64(xtl, 0);
}
+
+static void gen_xsxsigdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(rt, rt, t0);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
#endif
#undef GEN_XX2FORM
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 2ea8ce4..c7791f8 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -118,6 +118,7 @@ GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
+GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.7.4
- [Qemu-ppc] [PATCH 08/14] target-ppc: Use correct precision for FPRF setting, (continued)
- [Qemu-ppc] [PATCH 08/14] target-ppc: Use correct precision for FPRF setting, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 07/14] target-ppc: Add xscvdphp, xscvhpdp, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 10/14] target-ppc: Add xscvqpdp instruction, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 03/14] target-ppc: Use float64 arg in helper_compute_fprf(), Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 13/14] target-ppc: Add xsxsigdp instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH 14/14] target-ppc: Add xsxsigqp instructions, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 12/14] target-ppc: Add xsxexpqp instruction, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 11/14] target-ppc: Add xsxexpdp instruction, Nikunj A Dadhania, 2017/01/05
- [Qemu-ppc] [PATCH 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, Nikunj A Dadhania, 2017/01/05
- Re: [Qemu-ppc] [PATCH 00/14] POWER9 TCG enablements - part10, David Gibson, 2017/01/05