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Re: [Qemu-ppc] [PATCH v1 5/9] target-ppc: implement xxextractuw instruct
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction |
Date: |
Fri, 9 Dec 2016 09:32:21 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Dec 07, 2016 at 11:54:58PM +0530, Nikunj A Dadhania wrote:
> xxextractuw: VSX Vector Extract Unsigned Word
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 31 +++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate/vsx-ops.inc.c | 5 +++++
> 4 files changed, 64 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 91bdfc3..940f81c 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -536,6 +536,7 @@ DEF_HELPER_2(xvrspic, void, env, i32)
> DEF_HELPER_2(xvrspim, void, env, i32)
> DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> +DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 7030f61..093c5ec 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2033,6 +2033,37 @@ VEXTRACT(uw, u32)
> VEXTRACT(d, u64)
> #undef VEXTRACT
>
> +#if defined(HOST_WORDS_BIGENDIAN)
> +#define XXEXTRACT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
You're already breaking out to a helper. Why not just pass the
element size in as a parameter. As a bonus that means you can
restrict the ifdef HOST_WORDS_BIGENDIAN to a couple of lines, instead
of the whole helper.
> +{ \
> + ppc_vsr_t xt, xb; \
> + uint32_t es = sizeof(xt.element[0]); \
Also, strictly speaking, this should be a size_t.
> + getVSR(xbn, &xb, env); \
> + memset(&xt, 0, sizeof(xt)); \
> + memcpy(&xt.u8[8 - es], &xb.u8[index], es); \
> + putVSR(xtn, &xt, env); \
> +}
> +#else
> +#define XXEXTRACT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
> +{ \
> + ppc_vsr_t xt, xb; \
> + uint32_t es = sizeof(xt.element[0]); \
> + uint32_t s = (16 - index) - es; \
> + \
> + getVSR(xbn, &xb, env); \
> + memset(&xt, 0, sizeof(xt)); \
> + memcpy(&xt.u8[8], &xb.u8[s], es); \
> + putVSR(xtn, &xt, env); \
> +}
> +#endif
> +XXEXTRACT(xxextractuw, u32)
> +#undef XXEXTRACT
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate/vsx-impl.inc.c
> b/target-ppc/translate/vsx-impl.inc.c
> index c691141..a9c07c9 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -1162,6 +1162,33 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> +#define VSX_EXTRACT(name) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + TCGv xt, xb; \
> + TCGv_i32 t0 = tcg_temp_new_i32(); \
> + uint8_t uimm = UIMM4(ctx->opcode); \
> + \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + if (uimm > 12) { \
> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
> + return; \
> + } \
> + xt = tcg_const_tl(xT(ctx->opcode)); \
> + xb = tcg_const_tl(xB(ctx->opcode)); \
> + tcg_gen_movi_i32(t0, uimm); \
> + gen_helper_##name(cpu_env, xt, xb, t0); \
> + tcg_temp_free(xb); \
> + tcg_temp_free(xt); \
> + tcg_temp_free_i32(t0); \
> +}
> +
> +VSX_EXTRACT(xxextractuw)
> +
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> #undef GEN_XX2IFORM
> diff --git a/target-ppc/translate/vsx-ops.inc.c
> b/target-ppc/translate/vsx-ops.inc.c
> index be446ae..3ce657d 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -45,6 +45,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0,
> PPC_NONE, fl2)
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
>
> +#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE,
> fl2), \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
> +
> #define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2)
> \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2),
> \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
> @@ -272,6 +276,7 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
> GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> +GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 1/9] target-ppc: implement lxvl instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 2/9] target-ppc: implement lxvll instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 3/9] target-ppc: implement stxvl instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 4/9] target-ppc: implement stxvll instructions, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction, Nikunj A Dadhania, 2016/12/07
- Re: [Qemu-ppc] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction,
David Gibson <=
- [Qemu-ppc] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction, Nikunj A Dadhania, 2016/12/07
- [Qemu-ppc] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions, Nikunj A Dadhania, 2016/12/07