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[Qemu-ppc] [PATCH 10/13] target-ppc: implement xsabsqp/xsnabsqp instruct
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From: |
Nikunj A Dadhania |
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Subject: |
[Qemu-ppc] [PATCH 10/13] target-ppc: implement xsabsqp/xsnabsqp instruction |
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Date: |
Mon, 5 Dec 2016 16:55:27 +0530 |
xsabsqp: VSX Scalar Absolute Quad-Precision
xsnabsqp: VSX Scalar Negative Absolute Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate/vsx-impl.inc.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 5 +++++
2 files changed, 40 insertions(+)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 07f1904..970d83c 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -639,6 +639,41 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ int xt = rD(ctx->opcode) + 32; \
+ int xb = rB(ctx->opcode) + 32; \
+ TCGv_i64 xbh, xbl, sgm; \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new_i64(); \
+ xbl = tcg_temp_new_i64(); \
+ sgm = tcg_temp_new_i64(); \
+ tcg_gen_mov_i64(xbh, cpu_vsrh(xb)); \
+ tcg_gen_mov_i64(xbl, cpu_vsrl(xb)); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ break; \
+ case OP_NABS: \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ break; \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
+ tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
+ tcg_temp_free_i64(xbl); \
+ tcg_temp_free_i64(xbh); \
+ tcg_temp_free_i64(sgm); \
+}
+
+VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
{ \
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 1285e0b..0216efe 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -96,12 +96,17 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0,
PPC_NONE, PPC2_VSX)
#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \
+GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300)
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.7.4
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 05/13] target-ppc: implement stxvl instruction, (continued)
- [Qemu-ppc] [PATCH 07/13] target-ppc: implement xxextractuw instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 09/13] target-ppc: implement stop instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 06/13] target-ppc: implement stxvll instructions, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 08/13] target-ppc: implement xxinsertw instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 10/13] target-ppc: implement xsabsqp/xsnabsqp instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH 11/13] target-ppc: implement xsnegqp instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 13/13] target-ppc: Add xxperm and xxpermr instructions, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 12/13] target-ppc: implement xscpsgnqp instruction, Nikunj A Dadhania, 2016/12/05
- Re: [Qemu-ppc] [PATCH ppc-for-2.9 00/13] POWER9 TCG enablements - part9, David Gibson, 2016/12/05