[Qemu-ppc] [PATCH v2 0/2] POWER9 TCG enablements - part6

[Nikunj A Dadhania]

This series contains 6 new instructions for POWER9 ISA3.0
   Vector Integer Negate 
   Vector Byte-Reverse

Patches:
02:
    vnegw: Vector Negate Word
    vnegd: Vector Negate Doubleword
03:
    xxbrh: VSX Vector Byte-Reverse Halfword
    xxbrw: VSX Vector Byte-Reverse Word
    xxbrd: VSX Vector Byte-Reverse Doubleword
    xxbrq: VSX Vector Byte-Reverse Quadword

Changelog:
v1:
* Remove unused 'mask' in the define
* Fix bug in xxbrq: should have used move as the last
  translate operation instead of bswap.

v0:
* Added temporary in xxbrq
* Use negate directly in place for computing 2's compliment
* Use int8_t instead for char
* Dropped "VSX Scalar Compare" as fpu_helper needs change 
  with regard to exception flag handling

Nikunj A Dadhania (2):
  target-ppc: implement vnegw/d instructions
  target-ppc: implement xxbr[qdwh] instruction

 target-ppc/helper.h                 |  2 +
 target-ppc/int_helper.c             | 12 ++++++
 target-ppc/translate.c              | 32 +++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  2 +
 target-ppc/translate/vmx-ops.inc.c  |  2 +
 target-ppc/translate/vsx-impl.inc.c | 77 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  8 ++++
 7 files changed, 135 insertions(+)

-- 
2.7.4