[Qemu-ppc] [PATCH v1 0/3] POWER9 TCG enablements - part6

[Nikunj A Dadhania]

This series contains 11 new instructions for POWER9 ISA3.0
   Vector Extend Sign
   Vector Integer Negate 
   Vector Byte-Reverse

Patches:
01:
    vextsb2w: Vector Extend Sign Byte To Word
    vextsh2w: Vector Extend Sign Halfword To Word
    vextsb2d: Vector Extend Sign Byte To Doubleword
    vextsh2d: Vector Extend Sign Halfword To Doubleword
    vextsw2d: Vector Extend Sign Word To Doubleword
02:
    vnegw: Vector Negate Word
    vnegd: Vector Negate Doubleword
03:
    xxbrh: VSX Vector Byte-Reverse Halfword
    xxbrw: VSX Vector Byte-Reverse Word
    xxbrd: VSX Vector Byte-Reverse Doubleword
    xxbrq: VSX Vector Byte-Reverse Quadword

Changelog:
* Added temporary in xxbrq
* Use negate directly in place for computing 2's compliment
* Use int8_t instead for char
* Dropped "VSX Scalar Compare" as fpu_helper needs change 
  with regard to exception flag handling

Nikunj A Dadhania (3):
  target-ppc: implement vexts[bh]2w and vexts[bhw]2d
  target-ppc: implement vnegw/d instructions
  target-ppc: implement xxbr[qdwh] instruction

 target-ppc/helper.h                 |  7 ++++
 target-ppc/int_helper.c             | 27 +++++++++++++
 target-ppc/translate.c              | 32 +++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  7 ++++
 target-ppc/translate/vmx-ops.inc.c  |  7 ++++
 target-ppc/translate/vsx-impl.inc.c | 77 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  8 ++++
 7 files changed, 165 insertions(+)

-- 
2.7.4