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Re: [Qemu-ppc] [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization
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Re: [Qemu-ppc] [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization for pseries |
Date: |
Mon, 10 Oct 2016 08:53:40 -0700 (PDT) |
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization for pseries
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
* [new tag] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
- [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
e147fe5 spapr: Improved placement of PCI host bridges in guest memory map
2858c98 spapr_pci: Add a 64-bit MMIO window
b5718f3 spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM
10b7f69 spapr_pci: Delegate placement of PCI host bridges to machine type
=== OUTPUT BEGIN ===
Checking PATCH 1/4: spapr_pci: Delegate placement of PCI host bridges to
machine type...
Checking PATCH 2/4: spapr: Adjust placement of PCI host bridge to allow > 1TiB
RAM...
Checking PATCH 3/4: spapr_pci: Add a 64-bit MMIO window...
WARNING: line over 80 characters
#100: FILE: hw/ppc/spapr_pci.c:1361:
+ error_setg(errp, "64-bit memory window address not specified for
PHB");
WARNING: line over 80 characters
#105: FILE: hw/ppc/spapr_pci.c:1366:
+ error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx"
(max 2 GiB)",
WARNING: line over 80 characters
#220: FILE: include/hw/pci-host/spapr.h:85:
+#define SPAPR_PCI_MEM32_WIN_SIZE ((1ULL <<32) -
SPAPR_PCI_MEM_WIN_BUS_OFFSET)
ERROR: spaces required around that '<<' (ctx:WxV)
#220: FILE: include/hw/pci-host/spapr.h:85:
+#define SPAPR_PCI_MEM32_WIN_SIZE ((1ULL <<32) -
SPAPR_PCI_MEM_WIN_BUS_OFFSET)
^
total: 1 errors, 3 warnings, 166 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/4: spapr: Improved placement of PCI host bridges in guest
memory map...
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#133: FILE: hw/ppc/spapr.c:2534:
+#define SPAPR_COMPAT_2_7 \
+ HW_COMPAT_2_7 \
+ { \
+ .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
+ .property = "mem_win_size", \
+ .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
+ }, \
+ { \
+ .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
+ .property = "mem64_win_size", \
+ .value = "0", \
+ },
ERROR: trailing whitespace
#146: FILE: hw/ppc/spapr.c:2547:
+ $
total: 2 errors, 0 warnings, 175 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
[Qemu-ppc] [RFC 3/4] spapr_pci: Add a 64-bit MMIO window, David Gibson, 2016/10/05
[Qemu-ppc] [RFC 4/4] spapr: Improved placement of PCI host bridges in guest memory map, David Gibson, 2016/10/05
[Qemu-ppc] [RFC 2/4] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM, David Gibson, 2016/10/05
Re: [Qemu-ppc] [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization for pseries,
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