Re: [Qemu-ppc] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip

[Cédric Le Goater]

On 10/07/2016 06:34 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:40AM +0200, Cédric Le Goater wrote:
>> The Processor Identification Register (PIR) is a register that holds a
>> processor identifier which is used for bus transactions (XSCOM) and
>> for processor differentiation in multiprocessor systems. It also used
>> in the interrupt vector entries (IVE) to identify the thread serving
>> the interrupts.
>>
>> P9 and P8 have some differences in the CPU PIR encoding.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
> 
> Reviewed-by: David Gibson <address@hidden>
> 
> Looks fine, although it's a bit hard to be sure since I haven't read
> the patches which actually use this yet.

This is used in the next patch when the pir of the PnvCore is initialized :

+        object_property_set_int(OBJECT(pnv_core),
+                                pcc->core_pir(chip, core_hwid),
+                                "pir", &error_fatal);

Then this "pir" property of the core is added as a property alias to 
PowerPCCPU, which uses it to initialize SPR_PIR.

Thanks,

C.