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Re: [Qemu-ppc] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction
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From: |
Nikunj A Dadhania |
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Subject: |
Re: [Qemu-ppc] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction |
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Date: |
Thu, 29 Sep 2016 07:49:00 +0530 |
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User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
>> + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
>> + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
>
> Why are you using t0?
Thought about dropping it, but wasn't sure if deposit_i64 would change it.
Regards,
Nikunj
[Qemu-ppc] [PATCH v5 5/9] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/28
[Qemu-ppc] [PATCH v5 4/9] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/09/28
[Qemu-ppc] [PATCH v5 7/9] target-ppc: add stxvh8x instruction, Nikunj A Dadhania, 2016/09/28
[Qemu-ppc] [PATCH v5 6/9] target-ppc: add lxvh8x instruction, Nikunj A Dadhania, 2016/09/28
[Qemu-ppc] [PATCH v5 8/9] target-ppc: add lxvb16x instruction, Nikunj A Dadhania, 2016/09/28