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Re: [Qemu-ppc] [PATCH v4 3/9] target-ppc: Implement mtvsrws instruction
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-ppc] [PATCH v4 3/9] target-ppc: Implement mtvsrws instruction |
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Date: |
Wed, 28 Sep 2016 09:04:58 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 |
On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote:
> + tcg_gen_andi_i64(tmp1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF);
> + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), tmp1, tmp1, 32, 32);
> + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode)));
The andi is not necessary; the deposit handles all masking. Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
[Qemu-ppc] [PATCH v4 6/9] target-ppc: add lxvh8x instruction, Nikunj A Dadhania, 2016/09/28