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[Qemu-ppc] [PULL 30/44] target-ppc: consolidate store conditional
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 30/44] target-ppc: consolidate store conditional |
Date: |
Thu, 22 Sep 2016 16:37:28 +1000 |
From: Nikunj A Dadhania <address@hidden>
Use tcg_gen_qemu_st store conditional instructions.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 58 +++++++++++++++++++++-----------------------------
1 file changed, 24 insertions(+), 34 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 618fe43..ecc1674 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3076,19 +3076,19 @@ LARX(lwarx, DEF_MEMOP(MO_UL))
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
- int reg, int size)
+ int reg, int memop)
{
TCGv t0 = tcg_temp_new();
tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
- tcg_gen_movi_tl(t0, (size << 5) | reg);
+ tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
tcg_temp_free(t0);
gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
}
#else
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
- int reg, int size)
+ int reg, int memop)
{
TCGLabel *l1;
@@ -3096,44 +3096,36 @@ static void gen_conditional_store(DisasContext *ctx,
TCGv EA,
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
-#if defined(TARGET_PPC64)
- if (size == 8) {
- gen_qemu_st64_i64(ctx, cpu_gpr[reg], EA);
- } else
-#endif
- if (size == 4) {
- gen_qemu_st32(ctx, cpu_gpr[reg], EA);
- } else if (size == 2) {
- gen_qemu_st16(ctx, cpu_gpr[reg], EA);
- } else {
- gen_qemu_st8(ctx, cpu_gpr[reg], EA);
- }
+ tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_reserve, -1);
}
#endif
-#define STCX(name, len) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv t0; \
- gen_set_access_type(ctx, ACCESS_RES); \
- t0 = tcg_temp_local_new(); \
- gen_addr_reg_index(ctx, t0); \
- if (len > 1) { \
- gen_check_align(ctx, t0, (len)-1); \
- } \
- gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
- tcg_temp_free(t0); \
-}
-
-STCX(stbcx_, 1);
-STCX(sthcx_, 2);
-STCX(stwcx_, 4);
+#define STCX(name, memop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv t0; \
+ int len = MEMOP_GET_SIZE(memop); \
+ gen_set_access_type(ctx, ACCESS_RES); \
+ t0 = tcg_temp_local_new(); \
+ gen_addr_reg_index(ctx, t0); \
+ if (len > 1) { \
+ gen_check_align(ctx, t0, (len) - 1); \
+ } \
+ gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
+ tcg_temp_free(t0); \
+}
+
+STCX(stbcx_, DEF_MEMOP(MO_UB))
+STCX(sthcx_, DEF_MEMOP(MO_UW))
+STCX(stwcx_, DEF_MEMOP(MO_UL))
#if defined(TARGET_PPC64)
/* ldarx */
LARX(ldarx, DEF_MEMOP(MO_Q))
+/* stdcx. */
+STCX(stdcx_, DEF_MEMOP(MO_Q))
/* lqarx */
static void gen_lqarx(DisasContext *ctx)
@@ -3216,8 +3208,6 @@ static void gen_stqcx_(DisasContext *ctx)
tcg_temp_free(EA);
}
-/* stdcx. */
-STCX(stdcx_, 8);
#endif /* defined(TARGET_PPC64) */
/* sync */
--
2.7.4
- [Qemu-ppc] [PULL 43/44] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, (continued)
- [Qemu-ppc] [PULL 43/44] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 26/44] target-ppc: convert st64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 23/44] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 08/44] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 22/44] target-ppc: consolidate load operations, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 27/44] target-ppc: convert st[16, 32, 64]r to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 14/44] adb.c: add support for QKeyCode, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 25/44] target-ppc: consolidate store operations, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 41/44] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 24/44] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 30/44] target-ppc: consolidate store conditional,
David Gibson <=
- [Qemu-ppc] [PULL 29/44] target-ppc: move out stqcx impementation, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 44/44] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 39/44] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 03/44] target-ppc: add vector insert instructions, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 05/44] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 38/44] target-ppc: tlbie/tlbivax should have global effect, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 37/44] target-ppc: add flag in check_tlb_flush(), David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 21/44] spapr_vscsi: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 07/44] target-ppc: add vector permute right indexed instruction, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 11/44] tests: add RTAS command in the protocol, David Gibson, 2016/09/22