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[Qemu-ppc] [PULL 53/66] target-ppc: add extswsli[.] instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 53/66] target-ppc: add extswsli[.] instruction |
Date: |
Tue, 6 Sep 2016 13:40:40 +1000 |
From: Nikunj A Dadhania <address@hidden>
extswsli : Extend Sign Word & Shift Left Immediate
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5fe7a9d..14f4b68 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2329,6 +2329,30 @@ static void gen_sradi1(DisasContext *ctx)
gen_sradi(ctx, 1);
}
+/* extswsli & extswsli. */
+static inline void gen_extswsli(DisasContext *ctx, int n)
+{
+ int sh = SH(ctx->opcode) + (n << 5);
+ TCGv dst = cpu_gpr[rA(ctx->opcode)];
+ TCGv src = cpu_gpr[rS(ctx->opcode)];
+
+ tcg_gen_ext32s_tl(dst, src);
+ tcg_gen_shli_tl(dst, dst, sh);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, dst);
+ }
+}
+
+static void gen_extswsli0(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 0);
+}
+
+static void gen_extswsli1(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 1);
+}
+
/* srd & srd. */
static void gen_srd(DisasContext *ctx)
{
@@ -6228,6 +6252,10 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
+GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
+GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
#endif
#if defined(TARGET_PPC64)
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
--
2.7.4
- [Qemu-ppc] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe, (continued)
- [Qemu-ppc] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 38/66] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 45/66] ppc: Speed up load/store multiple, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 29/66] ppc: Make tlb_fill() use new exception helper, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 53/66] target-ppc: add extswsli[.] instruction,
David Gibson <=
- [Qemu-ppc] [PULL 48/66] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 40/66] ppc: Speed up dcbz, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 27/66] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 64/66] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 01/66] xics_kvm: drop extra checking of kernel_xics_fd, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 05/66] target-ppc: adding addpcis instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 10/66] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 55/66] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 56/66] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/05