Re: [Qemu-ppc] [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction

[Richard Henderson]

On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote:
> +static void gen_maddld(DisasContext *ctx)
> +{
> +    TCGv_i64 lo = tcg_temp_new_i64();
> +    TCGv_i64 hi = tcg_temp_new_i64();
> +    TCGv_i64 t1 = tcg_temp_new_i64();
> +    TCGv_i64 t2 = tcg_temp_new_i64();
> +    TCGv_i64 zero = tcg_const_i64(0);
> +    TCGv_i64 neg = tcg_const_i64(-1);
> +
> +    if (Rc(ctx->opcode)) {
> +        tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
> +                          cpu_gpr[rB(ctx->opcode)]);
> +        tcg_gen_movi_i64(t2, -1);
> +        tcg_gen_movcond_i64(TCG_COND_GE, t2, cpu_gpr[rC(ctx->opcode)], zero, 
> zero, neg);
> +    }
> +    tcg_gen_mov_i64(t1, zero);
> +    tcg_gen_add2_i64(cpu_gpr[rD(ctx->opcode)], t1, lo, hi, 
> cpu_gpr[rC(ctx->opcode)], t2);
> +    tcg_temp_free_i64(lo);
> +    tcg_temp_free_i64(hi);
> +    tcg_temp_free_i64(t1);
> +    tcg_temp_free_i64(t2);
> +    tcg_temp_free_i64(zero);
> +    tcg_temp_free_i64(neg);
> +}

None of this double-word arithmetic is required.
This produces a truncated 64-bit result; the high bits aren't used.

Why the conditional on Rc?  I see no special case for R0.


r~