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[Qemu-ppc] [PATCH 6/9] ppc: Fix mtmsr decoding
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 6/9] ppc: Fix mtmsr decoding |
Date: |
Tue, 7 Jun 2016 12:50:25 +1000 |
We had code to handle the L bit in the opcode but we didn't
allow it in the decode mask.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b34289f..3255184 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9944,7 +9944,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801,
PPC_MISC),
#if defined(TARGET_PPC64)
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
#endif
-GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
+GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
--
2.5.5
- [Qemu-ppc] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 6/9] ppc: Fix mtmsr decoding,
Benjamin Herrenschmidt <=
- [Qemu-ppc] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 7/9] ppc: Fix slbia decode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, Benjamin Herrenschmidt, 2016/06/06