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Re: [Qemu-ppc] [Qemu-devel] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia
From: |
Thomas Huth |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia privilege |
Date: |
Sat, 4 Jun 2016 10:24:28 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 |
On 03.06.2016 14:11, Cédric Le Goater wrote:
> commit 74693da98894 ('ppc: tlbie, tlbia and tlbisync are HV only')
> introduced some extra checks on the instruction privilege. slbia was
> changed wrongly and hrfid, tlbia were forgotten.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
> target-ppc/translate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index ad262523abca..776343170a53 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -4108,7 +4108,7 @@ static void gen_hrfid(DisasContext *ctx)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> /* Restore CPU state */
> - if (unlikely(!ctx->hv)) {
> + if (unlikely(ctx->pr || !ctx->hv)) {
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
> @@ -4845,7 +4845,7 @@ static void gen_tlbia(DisasContext *ctx)
> #if defined(CONFIG_USER_ONLY)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> - if (unlikely(ctx->pr)) {
> + if (unlikely(ctx->pr || !ctx->hv)) {
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
> @@ -4913,7 +4913,7 @@ static void gen_slbia(DisasContext *ctx)
> #if defined(CONFIG_USER_ONLY)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> - if (unlikely(ctx->pr || !ctx->hv)) {
> + if (unlikely(ctx->pr)) {
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
I just double-checked the PowerISA 2.07, and you're right, hrfid and
tlbia are hypervisor-privileged, slbia is only "normal" privileged.
Reviewed-by: Thomas Huth <address@hidden>
- [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode, Cédric Le Goater, 2016/06/03
- [Qemu-ppc] [PATCH 1/3] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, Cédric Le Goater, 2016/06/03
- [Qemu-ppc] [PATCH 2/3] ppc: Better figure out if processor has HV mode, Cédric Le Goater, 2016/06/03
- [Qemu-ppc] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia privilege, Cédric Le Goater, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 3/3] ppc: fix hrfid, tlbia and slbia privilege,
Thomas Huth <=
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Mark Cave-Ayland, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Cédric Le Goater, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Mark Cave-Ayland, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Cedric Le Goater, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Mark Cave-Ayland, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Mark Cave-Ayland, 2016/06/03
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Cédric Le Goater, 2016/06/03
Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode, Cédric Le Goater, 2016/06/05