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[Qemu-ppc] [PULL 33/39] target-ppc: Use actual page size encodings from
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 33/39] target-ppc: Use actual page size encodings from HPTE |
Date: |
Fri, 29 Jan 2016 16:07:05 +1100 |
At present the 64-bit hash MMU code uses information from the SLB to
determine the page size of a translation. We do need that information to
correctly look up the hash table. However the MMU also allows a
possibly larger page size to be encoded into the HPTE itself, which is used
to populate the TLB. At present qemu doesn't check that, and so doesn't
support the MPSS "Multiple Page Size per Segment" feature.
This makes a start on allowing this, by adding an hpte_page_shift()
function which looks up the page size of an HPTE. We use this to validate
page sizes encodings on faults, and populate the qemu TLB with larger
page sizes when appropriate.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
---
target-ppc/mmu-hash64.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 60 insertions(+), 3 deletions(-)
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index b784791..ee1e8bf 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -21,6 +21,7 @@
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "qemu/error-report.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"
@@ -474,12 +475,50 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
return pte_offset;
}
+static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
+ uint64_t pte0, uint64_t pte1)
+{
+ int i;
+
+ if (!(pte0 & HPTE64_V_LARGE)) {
+ if (sps->page_shift != 12) {
+ /* 4kiB page in a non 4kiB segment */
+ return 0;
+ }
+ /* Normal 4kiB page */
+ return 12;
+ }
+
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const struct ppc_one_page_size *ps = &sps->enc[i];
+ uint64_t mask;
+
+ if (!ps->page_shift) {
+ break;
+ }
+
+ if (ps->page_shift == 12) {
+ /* L bit is set so this can't be a 4kiB page */
+ continue;
+ }
+
+ mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
+
+ if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
+ return ps->page_shift;
+ }
+ }
+
+ return 0; /* Bad page size encoding */
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
ppc_slb_t *slb;
+ unsigned apshift;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
int pp_prot, amr_prot, prot;
@@ -543,6 +582,18 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr,
qemu_log_mask(CPU_LOG_MMU,
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
+ /* Validate page size encoding */
+ apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
+ if (!apshift) {
+ error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
+ " @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
+ /* Not entirely sure what the right action here, but machine
+ * check seems reasonable */
+ cs->exception_index = POWERPC_EXCP_MCHECK;
+ env->error_code = 0;
+ return 1;
+ }
+
/* 5. Check access permissions */
pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
@@ -595,10 +646,10 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr,
/* 7. Determine the real address from the PTE */
- raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, eaddr);
+ raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
- prot, mmu_idx, TARGET_PAGE_SIZE);
+ prot, mmu_idx, 1ULL << apshift);
return 0;
}
@@ -609,6 +660,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong addr)
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
+ unsigned apshift;
if (msr_dr == 0) {
/* In real mode the top 4 effective address bits are ignored */
@@ -625,7 +677,12 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong addr)
return -1;
}
- return deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, addr)
+ apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
+ if (!apshift) {
+ return -1;
+ }
+
+ return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
& TARGET_PAGE_MASK;
}
--
2.5.0
- [Qemu-ppc] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register(), (continued)
- [Qemu-ppc] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 09/39] spapr: Remove abuse of rtas_ld() in h_client_architecture_support, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 11/39] ppc: Clean up error handling in ppc_set_compat(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 14/39] pseries: Clean up error handling in spapr_vga_init(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 27/39] cuda.c: return error for unknown commands, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 22/39] target-ppc: gdbstub: introduce avr_need_swap(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 13/39] pseries: Clean up error handling in spapr_validate_node_memory(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 26/39] pseries: Allow TCG h_enter to work with hotplugged memory, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 23/39] target-ppc: gdbstub: fix altivec registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 37/39] target-ppc: Helper to determine page size information from hpte alone, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 33/39] target-ppc: Use actual page size encodings from HPTE,
David Gibson <=
- [Qemu-ppc] [PULL 25/39] target-ppc: gdbstub: Add VSX support, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 28/39] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 20/39] target-ppc: rename and export maybe_bswap_register(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 34/39] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 32/39] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/29