Re: [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions

[Alexander Graf]

On 02.07.15 06:44, Anton Blanchard wrote:
> We are setting SRR0 to the instruction before the one causing the
> unaligned exception. A quick testcase:
> 
> . = 0x100
> .globl _start
> _start:
>       /* Cause a 0x600 */
>       li      3,0x1
>       stwcx.  3,0,3
> 1:    b       1b
> 
> . = 0x600
> 1:    b       1b
> 
> Built into something we can load as a BIOS image:
> 
> gcc -mbig -c test.S
> ld -EB -Ttext 0x0 -o test test.o
> objcopy -O binary test test.bin
> 
> Run with:
> 
> qemu-system-ppc64 -nographic -bios test.bin
> 
> Shows an incorrect SRR0 (points at the li):
> 
> SRR0 0000000000000100
> 
> With the patch we get the correct SRR0:
> 
> SRR0 0000000000000104
> 
> Signed-off-by: Anton Blanchard <address@hidden>

Thanks, applied to ppc-next.


Alex