qemu-ppc
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] pci: allow 0 address for PCI IO/M


From: Peter Maydell
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] pci: allow 0 address for PCI IO/MEM regions
Date: Thu, 23 Jul 2015 22:19:12 +0100

On 23 July 2015 at 22:10, Michael S. Tsirkin <address@hidden> wrote:
> On Thu, Jul 23, 2015 at 10:00:30PM +0100, Peter Maydell wrote:
>> (Also, none of our PCI device models actually try to do
>> the "BAR at zero means I won't respond" behaviour, which
>> presumably they might do in real life.)

> Maybe some devices do this, but I'm guessing not all of them,
> since there's no hint in the pci spec that they should.

I think this depends on which version of the spec you
read. The PCI 2.1 spec has an implementation note that
says:

# Note: A Base Address register does not contain a valid
# address when it is equal to "0".

which could be taken to mean "0 is invalid". A 'note'
isn't part of the formal spec, of course (and the text
got deleted from later spec revisions), but that
doesn't mean implementers necessarily ignored it.

There's an ancient Torvalds rant where he claims
in passing that "a lot" of devices do this:
http://yarchive.net/comp/linux/zero.html

-- PMM



reply via email to

[Prev in Thread] Current Thread [Next in Thread]