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[Qemu-ppc] [PATCH 4/7] target-ppc: mffs. Should Set CR1 from FPSCR Bits
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 4/7] target-ppc: mffs. Should Set CR1 from FPSCR Bits |
Date: |
Mon, 3 Nov 2014 14:01:14 -0600 |
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9653ba9..0247af5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2512,7 +2512,9 @@ static void gen_mffs(DisasContext *ctx)
}
gen_reset_fpstatus();
tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr();
+ }
}
/* mtfsb0 */
--
1.7.1
- [Qemu-ppc] [PATCH 0/7] target-ppc: Assorted Floating Point Bugs and Cleanup, Tom Musta, 2014/11/03
- [Qemu-ppc] [PATCH 1/7] target-ppc: VXSQRT Should Not Be Set for NaNs, Tom Musta, 2014/11/03
- [Qemu-ppc] [PATCH 6/7] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf, Tom Musta, 2014/11/03
- [Qemu-ppc] [PATCH 4/7] target-ppc: mffs. Should Set CR1 from FPSCR Bits,
Tom Musta <=
- [Qemu-ppc] [PATCH 5/7] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr, Tom Musta, 2014/11/03
- [Qemu-ppc] [PATCH 3/7] target-ppc: Fix Floating Point Move Instructions That Set CR1, Tom Musta, 2014/11/03
- [Qemu-ppc] [PATCH 7/7] target-ppc: Eliminate set_fprf Argument From helper_compute_fprf, Tom Musta, 2014/11/03
- Re: [Qemu-ppc] [PATCH 0/7] target-ppc: Assorted Floating Point Bugs and Cleanup, Paolo Bonzini, 2014/11/04