[Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

This patch series enable floating point instruction in 440x5 CPUs 
which have the capabilities to have optional APU FPU.

1) Add floating point standard insns flag to 440x5 in case there is an apu fpu.
2) Define a new floating point insns flag for operation 
previously reserved to 64 bits proc (fcfid, fctid, fctidz)
3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 
restrictions
*** BLURB HERE ***

Pierre Mallard (3):
  target-ppc : Add floating point ability to 440x5 PPC CPU
  target-ppc : Add PPC_FLOAT_64 flag to instructions type
  target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and
    remove their TARGET_PPC64 restriction

 target-ppc/cpu.h            |    7 +++++--
 target-ppc/fpu_helper.c     |    7 +++----
 target-ppc/helper.h         |    6 ++++--
 target-ppc/translate.c      |   20 ++++++++++++--------
 target-ppc/translate_init.c |    4 ++++
 5 files changed, 28 insertions(+), 16 deletions(-)

-- 
1.7.10.4