Re: [Qemu-ppc] [PATCH v3 19/24] target-ppc: Add POWER8's TM SPRs

[Alexander Graf]

On 27.05.14 12:37, Alexey Kardashevskiy wrote:
> This adds TM (Transactional Memory) SPRs.
>
> Since TEXASRU is an upper half of TEXASR, special handling is needed here.
> This adds two helpers: spr_read_prev_upper32()/spr_write_prev_upper32().
> They read/write upper half of a previous 64bit SPR. Since TEXASR and
> TEXASRU have consequent numbers, that works. These will be used later
> for other SPRs as well.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
>   target-ppc/cpu.h            |  4 ++++
>   target-ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 49 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index c2a84fd..778b7d7 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1260,6 +1260,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>   #define SPR_MPC_EIE           (0x050)
>   #define SPR_MPC_EID           (0x051)
>   #define SPR_MPC_NRI           (0x052)
> +#define SPR_TFHAR             (0x080)
> +#define SPR_TFIAR             (0x081)
> +#define SPR_TEXASR            (0x082)
> +#define SPR_TEXASRU           (0x083)
>   #define SPR_UCTRL             (0x088)
>   #define SPR_MPC_CMPA          (0x090)
>   #define SPR_MPC_CMPB          (0x091)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 0682739..9dda60e 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -117,6 +117,30 @@ static void spr_access_nop(void *opaque, int sprn, int 
> gprn)
>   
>   #endif
>   

I guess these want to live inside an #ifdef CONFIG_PPC64? Did the code 
compile with ppc-softmmu? Did it compile with --enable-tcg-debug?

> +static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
> +{
> +    TCGv_i32 spr32 = tcg_temp_new_i32();
> +    TCGv spr = tcg_temp_new();

TCGv_i64 spr = tcg_temp_new_i64();

> +
> +    gen_load_spr(spr, sprn - 1);
> +    tcg_gen_trunc_shr_i64_i32(spr32, spr, 32);
> +    tcg_gen_ext32u_tl(cpu_gpr[gprn], spr32);
> +
> +    tcg_temp_free(spr);

tcg_temp_free_i64(spr)

> +    tcg_temp_free(spr32);

tcg_temp_free_i32(spr32);

> +}
> +
> +static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
> +{
> +    TCGv spr = tcg_temp_new();

The same goes here - or you use tcg_gen_deposit_tl below, then the TCGv 
can stay at tl size (if you omit size information it means tl).


Alex

> +
> +    gen_load_spr(spr, sprn - 1);
> +    tcg_gen_deposit_i64(spr, spr, cpu_gpr[gprn], 32, 32);
> +    gen_store_spr(sprn - 1, spr);
> +
> +    tcg_temp_free(spr);
> +}
> +
>   /* SPR common to all PowerPC */
>   /* XER */
>   static void spr_read_xer (void *opaque, int gprn, int sprn)
> @@ -7598,6 +7622,26 @@ static void gen_spr_power8_branch_control(CPUPPCState 
> *env)
>                    0x00000000);
>   }
>   
> +static void gen_spr_power8_tm(CPUPPCState *env)
> +{
> +    spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> +                     &spr_read_generic, &spr_write_generic,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_TFHAR, 0x00000000);
> +    spr_register_kvm(env, SPR_TFIAR, "TFIAR",
> +                     &spr_read_generic, &spr_write_generic,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_TFIAR, 0x00000000);
> +    spr_register_kvm(env, SPR_TEXASR, "TEXASR",
> +                     &spr_read_generic, &spr_write_generic,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_TEXASR, 0x00000000);
> +    spr_register(env, SPR_TEXASRU, "TEXASRU",
> +                 &spr_read_prev_upper32, &spr_write_prev_upper32,
> +                 &spr_read_prev_upper32, &spr_write_prev_upper32,
> +                 0x00000000);
> +}
> +
>   static void gen_spr_power8_common(CPUPPCState *env)
>   {
>       spr_register_kvm(env, SPR_FSCR, "FSCR",
> @@ -7647,6 +7691,7 @@ static void init_proc_POWER(CPUPPCState *env, int version)
>       }
>       if (version >= BOOK3S_CPU_POWER8) {
>           gen_spr_power8_branch_control(env);
> +        gen_spr_power8_tm(env);
>           gen_spr_power8_pmu(env);
>           gen_spr_power8_common(env);
>       }