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Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] PPC: Clean up DECR implementation

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] PPC: Clean up DECR implementation
Date: Tue, 08 Apr 2014 21:58:05 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130910 Thunderbird/17.0.9

On 04/08/2014 09:56 PM, Tom Musta wrote:
On 4/6/2014 3:55 PM, Alexander Graf wrote:

@@ -806,6 +838,10 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t 
      tb_env = g_malloc0(sizeof(ppc_tb_t));
      env->tb_env = tb_env;
      tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
+    if (env->insns_flags & PPC_SEGMENT_64B) {
+        /* All Book3S 64bit CPUs implement level based DEC logic */
+        tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
+    }
      /* Create new timer */
      tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, 
      if (0) {
Equating Book3S with PPC_SEGMENT_64B is clever ... is it too clever?  
Especially since
the SLB Bridge is in the phased-out category and consequently we should expect 
Book3S implementations to not support this instruction category.

Maybe it's too clever :). I'm very open to suggestions on how to figure this out otherwise. Or maybe we should just rework the way timers get created and make them be part of the core itself?


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